M.T. French

Measurements of transistors and silicon microstrip detector readout circuits in the Harris AVLSIRA rad-hard CMOS process

Abstract The RD20 collaboration has been developing silicon detectors and front end electronics for inner tracking applications at the proposed Large Hadron Collider (LHC) accelerator at CERN. Prototype amplifier circuits and test structures have been designed and fabricated in a radiation hard bulk CMOS technology (Harris AVLSIRA). Results from measurements of individual transistors and circuits from the first fabrication run in this process are presented, before and after irradiation. The noise performance of the prototype amplifiers is compared with predictions from the transistor noise spectrum measurements, and the optimised performance is predicted.

A fast integrated readout system for a cathode pad photon detector

Abstract A fast integrated electronic chain is presented to read out the cathode pad array of a multiwire photon detector for a fast RICH counter. Two VLSI circuits have been designed and produced. An analog eight-channel, low-noise, fast, bi-polar current preamplifier-amplifier and discriminator chip serves as the front-end detection electronics. It has an rms equivalent noise current of 10 nA, 50 MHz bandwidth with 10 mW of power consumption per channel. Two analog chips are coupled to a digital sixteen-channel CMOS readout chip, operating at 20 MHz with a power consumption of 6 mW per channel. Readout of a 4000 pad sector requires 2–3 μs, depending on the number of hit pads. The full RICH counter is made up of many such sectors, read out in parallel. The minimum time needed to separate successive hits on the same pad is 70 ns. The conception of the digital chip and its properties are fully presented in this report. The analog chip is described in less detail since it will be fully covered in a forthcoming paper.

Radiation hard electronics for LHC

Abstract A CMOS front end electronics chain is being developed by the RD20 collaboration for microstrip detector readout at LHC. It is based on a preamplifier and CR-RC filter, analogue pipeline and an analogue signal processor. Amplifiers and transistor test structures have been constructed and evaluated in detail using a Harris 1.2 μm radiation hardened CMOS process. Progress with larger scale elements, including 32 channel front end chips, is described. A radiation hard 128 channel chip, with a 40 MHz analogue multiplexer, is to be submitted for fabrication in July 1994 which will form the basis of the readout of the tracking system of the CMS experiment.

Beam test performance of the APV5 chip

Abstract The performance of the latest prototype of the radiation hard front end chip to be used by the CMS collaboration for analogue readout of the microstrip tracker has been evaluated with a silicon microstrip detector in a beam at CERN. The circuit, developed by the RD20 collaboration, consists of 128 channels of amplifier, pipeline memory, analogue signal processor and a serial multiplexer. As a result of these studies improvements in the circuit design have been devised which will be implemented in the next version.

Beam test of a prototype readout system for precision tracking detectors at LHC

Abstract A prototype of a readout system developed for high spatial precision tracking detectors at LHC has been tested in a beam at CERN. It is based on a radiation hard CMOS front-end chip which includes signal amplification, storage in an analogue delay line and a deconvolution filter. Data were transferred from the front-end chip using an analogue fibre optic link employing a novel reflective electro-optic modulator and continuous laser light source remote from the detector. This is the first time such a system has been used in an experimental environment and is the basis of the system proposed for the CMS experiment at LHC.