Mona Safar

A reconfigurable, pipelined, conflict directed jumping search SAT solver

Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a five-stage pipelined SAT solver. SAT solving is broken into five stages: variable decision, variable effect fetch, clause evaluation, conflict detection, and conflict analysis. The solver performs a novel search algorithm combining state-of-the-art SAT solvers advanced techniques: non-chronological backjumping, dynamic backtracking and learning without explicit traversal of implication graph. SAT instance information is stored into FPGA block RAMs avoiding synthesizing overhead for each instance. The proposed solver achieves up to 70× speedup over other hardware SAT solvers with 200× less resource utilization.

A Shift Register based Clause Evaluator for Reconfigurable SAT Solver

Several approaches have been proposed to accelerate the NP-complete Boolean satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator, where each clause is modeled as a shift register that is either right shifted, left shifted, or standstill according to whether the current assigned variable value satisfy, unsatisfy, or does not effect the clause, respectively. For a given problem instance, the effect of the value of each of its variables on its SAT formula is loaded in the FPGA on-chip memory. This results in less configuration effort and fewer hardware resources than other available SAT solvers. Also, we present a new approach for implementing conflict analysis based on a conflicting variables accumulator and priority encoder to determine backtrack level. Using these two new ideas, we implement an FPGA based SAT solver performing depth-first search with non-chronological conflict directed backtracking. We compare our SAT solver with other solvers through instances from DIMACS benchmarks suite

System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation

System-on-chip designs became complex. As such, tracing complex sequential circuits over many clock cycles is not a simple process any more. Due to that, many mistakes can be made while writing assertions. In this paper, a new effective methodology is proposed to debug errors in an assertion assuming that there is no error in the design or the test bench. The proposed methodology is based on an innovated propagate-and-repeat algorithm, an enhanced mutation model, and a new three-state visual representation. A multi-core processing utilizing an efficient event scheduling engine is used to speed up the methodology analysis time. Experimental results show the efficiency of the proposed methodology in determining the errors in the assertion and on providing more information on design behavior.

FPGA-Based SAT Solver

The Boolean satisfiability problem (SAT) is a central problem in artificial intelligence, mathematical logic and computing theory with wide range of practical applications. Being an NP-complete problem, the used SATs solving algorithm execution time influences the performance of SAT-based applications. FPGAs represent a promising technology for accelerating SAT solvers. In this paper, we present an FPGA-based SAT solver based on depth-first search. Our architecture exploits the fine granularity and massive parallelism of FPGAs to evaluate the SAT formula and perform conflict diagnosis. Conflict diagnosis helps pruning the search space by allowing nonchronological conflict directed backtracking. Our architecture modularity enables reflecting a specific SAT instance through memory initialization reducing hardware compilation overhead. The gain in performance is validated through DIMACS benchmarks suite

A design methodology for system level synthesis of multi-core system architectures

A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and HW/SW partition. The back end engine generates a SystemC simulation model using a well-known commercial tool model generation library. The viability and potential of the approach is demonstrated by a case study.

TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip

Easy, efficient, and automated technique for rapid architectural exploration is achieved using Transaction Level Modeling (TLM) methodology. Architecture evaluation is performed in early stage of the design. An approach for TLM architecture exploration of multi-core systems is presented. Starting with a Task Precedence Graphs (TPG) as a design entry, different architectures with different number of processor cores, number of busses and task-to-processor/channel-to-bus mapping are rapidly explored. The viability and potential of the proposed approach is demonstrated.

FPGA based accelerator for 3-SAT conflict analysis in SAT solvers

We present an FPGA-based accelerator for 3-SAT clause evaluation and conflict diagnosis and propose an approach to incorporate it in solving the Combinational Equivalence Checking problem. SAT binary clauses are mapped onto an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict analyzer on FPGA.

A novel conflict directed jumping algorithm for hardware-based SAT solvers

Much of the performance improvement achieved by state-of-the-art SAT solvers is related to the implementation of conflict analysis which enables the solver to perform nonchronological conflict-based backjumping and learn new clauses. However, these techniques have been ignored by the majority of hardware SAT solvers or are executed on some coupled software running on an attached host processor. In this paper, we present a reconfigurable hardware SAT solver that performs a search algorithm combining the advanced techniques: non-chronological backjumping, dynamic backtracking and learning. The whole execution is done in hardware eliminating any runtime communication with the host processor. The feasibility of the proposed approach is experimented through instances from the DIMACS benchmarks suite.

A Reconfigurable Five-Stage Pipelined SAT Solver

Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a five stage pipelined SAT solver. The first stage is a variable decider that, in the normal flow, assigns a free variable from a set of statically pre-ordered variables. In case of conflict, where one or more of the SAT CNF clauses is unsatisfied,the highest ordered variable from a pool of conflicting variables is reassigned or freed. The second stage fetches the effect of the current assigned variable on the SAT instance clauses from a memory pre-initialized with the effect of each variable on all clauses. This data is fed to the next stage, the clause evaluator. The fourth stage is the conflict detector that detects if there is a conflict and, if there is, it detects the index of the first unsatisfied clause.The last stage fetches the conflicting variables (variables in the unsatisfied clause) from a memory containing variables associated with each clause. Our approach’s feasibility is evaluated through instances from the DIMACS benchmarks suite. Pipelining allows retaining same clock frequency of an equivalent non-pipelined implementation while achieving an average of three times speedup in performance.

Hardware based algorithm for conflict diagnosis in SAT solver

The Boolean satisfiability problem (SAT) is an NP-complete problem so software SATs solving algorithm execution time influences the performance of SAT- based CAD tools. In this paper, we present a new approach for implementing conflict analysis based on a conflicting variables accumulator and priority encoder to determine backtrack level Using this approach, we implement an FPGA-based SAT solver performing depth- first search with conflict directed nonchronological backtracking. We compare our SAT solver with other SAT solvers through instances from DIMACS benchmarks suite.