M. Y. A. Yousif

CMOS considerations in nanoelectromechanical carbon nanotube-based switches.

In this paper, we focus on critical issues directly related to the viability of carbon nanotube-based nanoelectromechanical switches, to perform their intended functionality as logic and memory elements, through assessment of typical performance parameters with reference to complementary metal-oxide-semiconductor devices. A detailed analysis of performance metrics regarding threshold voltage control, static and dynamic power dissipation, speed, and integration density is presented. Apart from packaging and reliability issues, these switches seem to be competitive in low power, particularly low-standby power, logic and memory applications.

Recent critical issues in Si/Si1−xGex/Si heterostructure FET devices

Abstract In this paper we present a summary of the most important critical issues in Si/Si 1− x Ge x p-type and n-type heterostructure field-effect transistors. The controversial issue of alloy scattering and the phenomenon of velocity overshoot are reviewed and discussed. Achievements and problems associated with channel engineering and the use of alternative gate electrodes and high- κ dielectric materials are also addressed.

Direct assessment of relaxation and defect propagation in different as-grown and in situ post-growth annealed thin Ge/Si and step-graded Si1−xGex/Si buffer layers

Abstract The strain-sensitive X-ray two-dimensional reciprocal space mapping diffractrometry (2D-RSM) is employed to investigate the relaxation parameters and defect propagation in various thin relaxed buffer layers (RBLs) having a pure Ge top. In addition, we also studied the effect of in situ post-growth thermal treatments at an early growth stage of RBLs with low and intermediate Ge fraction. Both direct Ge epitaxy and multi-layer step-graded epitaxy have been adopted to grow these RBLs using chemical vapor deposition (CVD) at elevated partial pressure (around 10 Torr), which implies a much higher growth rate than RBLs grown using ultra-high vacuum CVD technique. Fully relaxed Ge top layers were obtained for both the direct Ge epitaxy, as well as for the step-graded technique. The results, when comparing these two techniques, favor the direct Ge epitaxy. However, the results of in situ post-growth annealing of the step-graded RBLs indicate a large reduction in the threading dislocations present in the grading regions without a change of relaxation degree or Ge% incorporation in that region.

Analysis of retrograded double quantum well p-type MOSFET

An analytical model for a double QW-PMOS is developed for the determination of the threshold voltages and an estimate of the hole densities in each conducting QW-channel including the silicon surface channel. Detailed analysis of the uncoupled retrograded double QW-PMOS is carried out with varying structural and physical parameters. The model adequately describes and predicts the best design choice of the double QW structure for optimum device performance. The procedure for the evaluation of the optimum structure is not just limited to QW-PMOSs in bulk silicon technology but can be also successfully applied for realizing QW-NMOS structures on relaxed buffer layers.

Threshold voltage and charge control considerations in double quantum wellSi/Si1−xGex p-type MOSFETs

Abstract A double quantum well Si/Si 1− x Ge x p-channel MOSFET (DQW-PMOS) is proposed and analyzed. Different Si/Si 1− x Ge x DQW designs both on bulk silicon and on silicon-on-insulator (SOI) substrates have been investigated using analytical and numerical approaches. Analytical modeling was used to investigate the threshold voltage of different channels. The numerical approach focused on the self-consistent 2D solution of the Schrodinger and Poisson equations to determine the confined hole density profile at different gate potentials. Both approaches reach the same conclusion regarding the best Si/Si 1− x Ge x DQW-PMOS design with respect to gate charge control and threshold voltage considerations. Among the investigated designs, the best hole confinement profile was for a structure with a 30%-Ge-content well at the substrate end (channel 1) and a 15%-Ge well close to the gate oxide (channel 2). Most of the confined holes in this structure are attributed to carriers from channel 1. For this design, the hole concentration profile in channel 1 was found to have a peak at the center of the channel. This retrograded DQW structure benefits from minimizing the mobility degradation due to interface scattering at the top Si/Si 1− x Ge x heterojunction. Therefore, the proposed structure of the DQW here shows that the built-in potential of the composite Si spacer layer and the top QW helps in the optimization of the hole distribution in the bottom QW. In addition, the above design offers better charge control compared to a structure with a 15%-Ge well at the substrate end and a 30%-Ge well close to the gate oxide. The implementation of the former structure leads to less 1/ f -noise and random telegraph signals. Hence, the structure is suitable for future analog applications.

Extremely small hole capture cross sections in HfO2∕HfxSiyOz∕p-Si structures

Defects in Al∕HfO2∕HfxSiyOz∕p-Si capacitors have been characterized using thermally stimulated current at temperatures between 30 and 300K. The hole activation energy and capture cross section were extracted from the results. The authors observed shallow traps that move with changing the discharging voltage, giving rise to activation energies in the range 0.03–0.14eV. Postmetallization anneal passivated these traps and a deeper trap appears with a significantly lower shift with the discharging voltage. Very small apparent capture cross sections (capture cross section times tunneling probability) have been extracted (10−26–10−18cm2). Simulations agree very well with experimental data.

On the performance of in situ B-doped P+ poly-Si1−xGex gate material for nanometer scale MOS technology

Abstract A study of in situ doped P+ poly-Si1−xGex gate material for the use in nanometer scale MOS technology is presented. P+ poly-Si1−xGex-gated MOS devices, with x=0%, 20%, or 35% and O2- and NO-grown ultrathin gate oxides (2.3–3.0 nm), were fabricated for this investigation. P+ poly-Si1−xGex-gated devices showed no appreciable difference in the direct tunneling current tolerance compared to P+ poly-Si-gated devices. According to SIMS results, no boron penetration is observed through the oxides, including oxides without nitrogen, after rapid thermal annealing at 900°C for 30 s, 1000°C for 10 s, and furnace annealing at 850°C for 40 min. Using C–V measurements, we found that in situ doping provides a more accurate way of assessing the effect of germanium on the work function of the gate and thus the threshold voltage adjustment for nanometer MOS devices.

Short-channel effects in Si/Si1−xGex retrograde double quantum well p-MOSFETs

Abstract Analytical investigation of short-channel effects in retrograde double quantum well Si 1− x Ge x -channel p-MOSFETs with effective channel lengths in the deep-submicron regime is addressed. The short-channel effects are accounted for by treating the short-channel device as a long-channel one with an apparently-reduced doping density which depends on the channel length and the gate/drain bias. The analysis focuses on the threshold voltage reduction, the gate voltage window, and the hole densities in the quantum wells. The model predicts significant differences in the threshold voltage reduction in the different channels of the device. The reduction is negligible in the surface parasitic channel, fairly small in the second quantum well (channel 2) below the surface channel, and relatively pronounced in the first quantum well closer to the depletion region (channel 1). Accordingly, the gate voltage window increases significantly. The hole density in the different channels has also been found to be appreciably influenced by decreasing channel length. The validity of the model is confirmed by comparing analytical calculations with available experimental and numerical results. These investigations can be used as guidelines for scaling Si/Si 1− x Ge x devices as they illustrate the degrees of freedom available to the Si/Si 1− x Ge x MOSFET designer.

ZrO2 Gate Dielectrics Prepared by E-beam Deposition of Zr and YSZ Films and Post Annealing Processes

In this paper we present the electrical performance of MOS capacitors with ZrO2 gate dielectric prepared by e-beam evaporation of zirconium and yttrium stabilized zirconia (YSZ) and subsequent thermal treatment. To this stage we have reached an equivalent oxide thickness (EOT) of 1.9 nm. The effect of post-oxidation annealing on Zr incorporation into the Si substrate is investigated. SIMS analysis showed no signs of Zr diffusion in the substrate at temperatures as high as 900°C and that significant diffusion occurs only at 1100°C

Process optimization for SiGe pMOSFETs using low temperature oxides on ultra-thin cap layers

We optimized the oxidation and annealing processes for SiGe quantum-well (QW) p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (pMOSFETs) to maintain the strain in the channel and to suppress or eliminate the Si cap layer parasitic conduction. We fabricated and investigated poly-Si gated MOS capacitors incorporating 2nm low-temperature furnace oxides and optimized ultra-thin Si-cap layers. For these structures, we found that a rapid thermal annealing (RTA) thermal budget of 950°C, 30s could serve as a proper choice for gate dopants activation.