O. Nur

Recent critical issues in Si/Si1−xGex/Si heterostructure FET devices

Abstract In this paper we present a summary of the most important critical issues in Si/Si 1− x Ge x p-type and n-type heterostructure field-effect transistors. The controversial issue of alloy scattering and the phenomenon of velocity overshoot are reviewed and discussed. Achievements and problems associated with channel engineering and the use of alternative gate electrodes and high- κ dielectric materials are also addressed.

dc characteristics of a nanoscale water-based transistor

We demonstrate a nanoscale water-based transistor. The presented nanoscale water-based transistor relies on the controlled modification of the pH in deionized water through the base applied electric field. The dc characteristics are presented and studied with a focus on the influence of the base applied electric field, the base electrode design, and their proximity to the sensing emitter and collector nanoelectrodes. The demonstrated water-based nanoscale device is of interest for many bioelectrical applications due to the biocompatibility and the wide usage and presence of water in biological systems.

Electrical and structural characterization of PtSi/p-Si1−xGex low Schottky barrier junctions prepared by co-sputtering

Schottky barrier junctions of PtSi/Si1−xGex were produced; the silicide was deposited by co-sputtering on defect-free well-calibrated strained-Si1−xGex (0⩽x⩽0.242) layers. This work is motivated by the fact that it is very difficult to control the formation of well-defined and well-controlled PtSi/Si1−xGex junctions by reacting Pt/Si1−xGex or by using a silicon cap layer. The Schottky barrier heights of these junctions were substantially lower than those of PtSi/Si junctions. Different characterization tools were employed for structural characterization. High-resolution multicrystal x-ray diffraction (HR-MCXRD) was used to investigate the sample quality and strain state of the molecular beam epitaxy (MBE) grown Si1−xGex layers and to accurately determine the Ge fraction in the fabricated junctions. Cross-sectional transmission electron microscopy (XTEM) was applied to investigate the interface roughness. The possible interlayer diffusion was investigated by secondary ion mass spectrometry (SIMS). The vari...

1/f noise characterization of Ir/p‐Si and Ir/p‐Si1−xGex low Schottky barrier junctions

The electrical noise properties of Ir/p‐Si and Ir/p‐Si1−xGex (x=0.14) Schottky junctions have been studied. The 1/f noise measurements were performed under forward bias over a wide temperature and frequency ranges. The effect of annealing on the noise properties of these junctions was also investigated. Annealed junction shows higher noise level. This was attributed to the defects formation at the metal/semiconductor interface. From the temperature dependence of the 1/f noise power density, an optimum operating temperature for as deposited and annealed junctions was found. The Hooge parameter, αH, is derived from the experimental data over a wide range of temperature for the deposited junctions. Values of 2.26×10−6 and 1.78×10−6 were obtained at room temperature for Ir/p‐Si and Ir/p‐Si1−xGex, respectively.

Direct assessment of relaxation and defect propagation in different as-grown and in situ post-growth annealed thin Ge/Si and step-graded Si1−xGex/Si buffer layers

Abstract The strain-sensitive X-ray two-dimensional reciprocal space mapping diffractrometry (2D-RSM) is employed to investigate the relaxation parameters and defect propagation in various thin relaxed buffer layers (RBLs) having a pure Ge top. In addition, we also studied the effect of in situ post-growth thermal treatments at an early growth stage of RBLs with low and intermediate Ge fraction. Both direct Ge epitaxy and multi-layer step-graded epitaxy have been adopted to grow these RBLs using chemical vapor deposition (CVD) at elevated partial pressure (around 10 Torr), which implies a much higher growth rate than RBLs grown using ultra-high vacuum CVD technique. Fully relaxed Ge top layers were obtained for both the direct Ge epitaxy, as well as for the step-graded technique. The results, when comparing these two techniques, favor the direct Ge epitaxy. However, the results of in situ post-growth annealing of the step-graded RBLs indicate a large reduction in the threading dislocations present in the grading regions without a change of relaxation degree or Ge% incorporation in that region.

Analysis of retrograded double quantum well p-type MOSFET

An analytical model for a double QW-PMOS is developed for the determination of the threshold voltages and an estimate of the hole densities in each conducting QW-channel including the silicon surface channel. Detailed analysis of the uncoupled retrograded double QW-PMOS is carried out with varying structural and physical parameters. The model adequately describes and predicts the best design choice of the double QW structure for optimum device performance. The procedure for the evaluation of the optimum structure is not just limited to QW-PMOSs in bulk silicon technology but can be also successfully applied for realizing QW-NMOS structures on relaxed buffer layers.

Silicon Germanium Strained Layers and Heterostructures

The integration of strained-Si1–xGex into Si technology has enhanced the performance and extended the functionality of Si based circuits. The improvement of device performance is observed in both AC as well as DC characteristics of these devices. The category of such devices includes field effect as well as bipolar families. Speed performance in some based circuits has reached limits previously dominated by III-V heterostructures based devices. In addition, for some optoelectronics applications including photodetectors it is now possible to easily integrate strained-Si1–xGex based optical devices into standard Silicon technology. The impact of integrating strained and relaxed Si1–xGex alloys into Si technology is important. It has lead to stimulate Si research as well as offers easy options for performances that requires very complicated and costly process if pure Si has to be used. In this paper we start by discussing the strain and stability of Si1–xGex alloys. The origin and the process responsible for transient enhanced diffusion (TED) in highly doped Si containing layers will be mentioned. Due to the importance of TED for thin highly doped Boron strained-Si1–xGex layers and its degrading consequences, possible suppression design methods will be presented. Quantum well pchannel MOSFETs (QW-PMOSFETs) based on thin buried QW are solution to the low speed and weak current derivability. Different aspects of designing these devices for a better performance are briefly reviewed. Other FETs based on tensile strained Si on relaxed Si1–xGex for n-channel and modulation doped field effect transistors (MODFETs) showed excellent performance. Record AC performance well above 200GHz for fmax is already observed and this record is expected to increase in the coming years. Heterojunction bipolar transistors (HPTs) with thin strained-Si1–xGex highly doped base have lead to optimize the performance of the bipolar technology for many applications easily. The strategies of design and the most important designs of HBTs for optimum AC as well as DC are discussed in details. This technology is now mature enough and that is manifested in the appearance in the market nowadays. Si1–xGex based FETs circuits compatible with standard Si CMOS processes are soon expected to appear in the market. Finally, we briefly discuss the recent advances in Si1–xGex based infrared photodetectors.

Threshold voltage and charge control considerations in double quantum wellSi/Si1−xGex p-type MOSFETs

Abstract A double quantum well Si/Si 1− x Ge x p-channel MOSFET (DQW-PMOS) is proposed and analyzed. Different Si/Si 1− x Ge x DQW designs both on bulk silicon and on silicon-on-insulator (SOI) substrates have been investigated using analytical and numerical approaches. Analytical modeling was used to investigate the threshold voltage of different channels. The numerical approach focused on the self-consistent 2D solution of the Schrodinger and Poisson equations to determine the confined hole density profile at different gate potentials. Both approaches reach the same conclusion regarding the best Si/Si 1− x Ge x DQW-PMOS design with respect to gate charge control and threshold voltage considerations. Among the investigated designs, the best hole confinement profile was for a structure with a 30%-Ge-content well at the substrate end (channel 1) and a 15%-Ge well close to the gate oxide (channel 2). Most of the confined holes in this structure are attributed to carriers from channel 1. For this design, the hole concentration profile in channel 1 was found to have a peak at the center of the channel. This retrograded DQW structure benefits from minimizing the mobility degradation due to interface scattering at the top Si/Si 1− x Ge x heterojunction. Therefore, the proposed structure of the DQW here shows that the built-in potential of the composite Si spacer layer and the top QW helps in the optimization of the hole distribution in the bottom QW. In addition, the above design offers better charge control compared to a structure with a 15%-Ge well at the substrate end and a 30%-Ge well close to the gate oxide. The implementation of the former structure leads to less 1/ f -noise and random telegraph signals. Hence, the structure is suitable for future analog applications.

Photoluminescence of pseudomorphic SiGe formed by 74Ge+ ion implantation in the overlayer of silicon-on-insulator material

A metastable SiGe-on-insulator structure is realized by a high-dose 74Ge+ ion implantation in the overlayer of silicon-on-insulator followed by solid phase epitaxial regrowth. Studies of the optical properties of the germanium-implanted and post-implantation annealed layers with 18% peak germanium concentration were carried out using photoluminescence (PL) spectroscopy. The electrical integrity of the strained layer was qualitatively inferred from the pseudo-mosfet characterization technique. The PL results show that the broadband (BB) emission related to germanium implantation damage can be completely eliminated by post-implantation thermal treatment. PL spectra and measured transconductance of the sample heat-treated at 500 °C indicate conclusively that a defect-free strained SiGe layer has been formed. However, samples heat-treated at higher temperatures show degradation in the charge carrier lifetime, a new BB emission with 0.816 eV peak energy and an emergence of defect related emission at 0.870 eV f...

Fermi-level pinning and Schottky barrier heights on epitaxially grown fully strained and partially relaxed n-type Si1−xGex layers

The Schottky barrier height on n-type Si1−xGex films has been studied as a function of the composition and strain relaxation. We have used electrical I–V measurements complemented by high-resolution x-ray measurements for assessment of the relaxation in the epilayers. In addition, Schottky barrier height on n-Si1−xGex films has also been investigated as a function of the metal work function. Our results shows that the barrier height on n-type Si1−xGex does not depend on either the Ge content or strain relaxation, but is sensitive to the metal work function. The experimental results indicate that the Fermi level is pinned to the conduction band and provide also the evidence that the pinning position of the Fermi level is metal work function dependent. This pinning behavior in metal Si1−xGex is opposed to that observed in metal/Si contacts, were the Fermi level is pinned either to the valence or conduction band depending on the metal work function. These findings regarding the relaxation independent barrier...