M. Y. Tsai

Thermal measurements and analyses of low-cost high-power LED packages and their modules

Abstract The thermal behaviors of high-power light emitting diode (LED) chip-on-plate (COP) package and module are investigated by experimental measurements (with LED junction temperature ( T j ) tester, thermocouples, and thermal imager), a thermal resistance circuit (TRC) method, a commercial finite element code (ANSYS), and a computational fluid dynamics code (CFdesign). Based on the experimental results, the thermal resistance of the COP package was found to be comparable to those for the commercial packages. Furthermore, it was also found that the T j and thermal resistances of the COP package and module, calculated from 2D ANSYS, 3D TRC and 3D CFdesign, are consistent well with those from the experiments. Besides, the uncertain equation-based convection coefficients used in ANSYS and TRC for the thermal analysis of the COP module were closely examined and discussed in detail by comparing with those from CFdesign analysis. Moreover, the validated ANSYS and CFdesign models were used for parametric studies of the COP module and further provided useful design parameters. Finally, the COP module under natural and forced convection conditions was studied, and the results showed that the junction-to-air thermal resistances are sensitive to the flow conditions, but not for thermal resistances from the junction to aluminum substrate and to heat sink.

Warpage Analysis of Flip-Chip PBGA Packages Subject to Thermal Loading

The aim of this paper was to measure and simulate the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260?C). In the experiments, a full-field shadow moirE? was used to measure real-time out-of-plane deformations (warpages) on the substrate and chip surfaces of the flip-chip packages under thermal heating and cooling conditions. A finite-element method (FEM) and Suhirs die-assembly theory, together with the measured material data (elastic moduli and coefficients of thermal expansion (CTEs) for organic substrates), were used to analyze the thermally induced deformations of the packages to gain insight into their mechanics. The strain gauge data used to determine the CTEs of the substrates also indicated that there was nearly no bending strain under thermal loading. The full-field warpages on the substrate surface of the packages from the shadow moirE? were documented under temperature loading. It was also found that there were different zero-warpage temperatures (which resulted in a variation of warpages at room temperature) for the four test packages during thermal loading, but they had similar warpage rates (the slope of warpage with respect to temperature). This might have been due to the creep of the underfill and the solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be well simulated or predicted by FEM and Suhirs theory. The key material properties (elastic moduli and CTEs for the substrate and underfill) that affect the maximum warpage of the package were thoroughly studied. It was found that, among these material properties, a low elastic modulus for the underfill can significantly reduce the maximum warpage, while its CTE is much less sensitive to warpage. Moreover, the substrate CTE affects the warpage of a package only with noncompliant underfills, while a typical substrate elastic modulus (ranging from 10 to 30 GPa) is insensitive to warpage, unless its value is lower than a few gigapascals.

Thermal analyses and measurements of low-Cost COP package for high-power LED

The high-power light emitting diode (LED), which features low-power consumption, longer life time and shorter response time, has a potential to replace the conventional general lighting, such as incandescent and fluorescent lamps. However, the LED issues, associated with high cost, high junction temperature, low luminous efficiency, and low reliability, have to be solved before gaining more market penetration. With special features of low-junction- temperature and low-cost design, a novel package for high- power LED, so called COP (chip on plate) package, is proposed in this study. The thermal behaviors of the COP package with and without a heat sink are investigated by experimental measurements (with LED junction temperature tester and thermal couples), a thermal resistance circuit (TRC) method, a finite element method (FEM) and a computational fluid dynamics (CFD) approach. The junction temperature (Tj) of the COP package was measured by the junction temperature tester and found to be comparable with those from commercial products, such as Crees, and Lumileds packages. Furthermore, the TRC and FEM were used for addressing the thermal fields of the COP package with and without a heat sink. The results of the thermal fields including the Tj from the experiments, FEM and TRC were found to be reasonably consistent under various input powers for the COP package, but not for the package with a heat sink. Moreover, the under-estimated thermal fields of the package with a heat sink from both FEM and TRC analyses were evaluated again by the CFD approach. The results indicate that the heat convection coefficients on the heat sink used the FEM and TRC analyses are higher than those calculated from the CFD. Finally, the reasonable and validated FEM and TRC models were used for parametric studies and their results show that the thermal conductivities of the die attach, chip substrate and package substrate (rather than the heat sink, chip, thermal grease and encapsulant) have an obvious effect on the Tj. In addition, for reducing the Tj, increasing the radius of the heat sink was found to be more beneficial than increasing the height.

Bump and Underfill Effects on Thermal Behaviors of Flip-Chip LED Packages: Measurement and Modeling

The goal of this paper is to experimentally and numerically study the thermal behaviors of flip-chip (FC) light-emitting diode (LED) packages with and without underfills and, furthermore, to compare it with conventional wire-bonding LED packages in order to understand its thermal dissipation mechanism. In experimental analyses, the junction temperature Tj and surface temperatures are measured by a junction temperature tester, thermal couples, and an infrared thermal imager, whereas the numerical analysis is carried out by an ANSYS simulation. After the validation of the simulation model with experimental results, the effects of FC bump number and underfill thermal conductivity on both Tj and thermal resistance Rth of the packages are investigated by this validated model. Furthermore, a simple model of effective thermal conductivity for a composite material of bumps and underfills is proposed for thermal analysis of the FCLED packages. Thermal results for the packages are presented and discussed in terms of volume fraction and thermal conductivity for bumps and underfills in this paper.

Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy) and aluminum pad. The purpose of this study is to measure and calculate thermally-induced deformations and stresses of flip-chip ball grid array (BGA) packages with a copper-pillar-bump interconnected chip inside. In the experiments, full-field Twyman-Green and moire interferometries are used to measure out-of-plane deformations on the chip surfaces of the package during a heating process and in-plane deformations on the cross-section surface of the package under a specific thermal loading, respectively. A finite element method (FEM) and Suhirs die-attachment assembly theory being validated by experimental data are employed to analyze the thermally-induced deformations and stresses of the package to gain insight into their mechanics. The experimental results show the zero-warpage temperature (or zero-stress temperatures) for this package is 115 °C due to the Tg of the underfill material rather than its curing temperature. It is also found that the thermal deformations of the package calculated by FEM and theory are well consistent with Twyman-Green and moire results. Furthermore, the local stresses around the critical copper-pillar bump joint region (especially at aluminum pad and low-k layer) where the possible failures occur during the TCT are investigated in detail through the validated FEM model. The results indicate that die/substrate thickness ratio would have significant effect on the stresses at aluminum pad and low-k layer, as well as package warpage and die stress.

Warpage and curvature determination of PCB with DIMM socket during reflow process by strain gage measurement

The purpose of this study is to in-situ measure the warpage of the PCB with surface-mount dual in-line memory module (DIMM) sockets during reflow process by using strain gages. In the experiments, a full-field shadow moire is used for measuring real-time out-of-plane deformations (or warpage) of the PCB with DIMM sockets under heating condition. A finite element method (FEM) is used to analyze the thermally-induced deformation of the PCB with DIMM sockets in order to ensure the validity of the measurement. The conventional strain gages and rosette are employed to in-situ measure the strains (even though they are in-plane strain data) in this PCB specimen during the solder reflow process. The results indicate that the strain gage measurement can be used to determine the bending strains of the PCB occurring during the solder reflow. These bending strains can be transferred to curvature data and global warpage. Therefore, it provides a real-time and easy-to-use method for monitoring the PCB warpage under temperature variation during the reflow process. In addition, the strain gage rosette has been successfully proved to be an enabling measurement of the local and full-field deformation of the PCB with DIMM socket during reflow process.

The impact of through silicon via proximity on CMOS device

As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes stresses on silicon near the TSV, the impact of TSV proximity on CMOS must be evaluated at various operation temperatures. In this paper, Cu-filled TSVs were fabricated in “via middle” process. The TSVs-induced mechanical stresses causing carrier mobility change that result in drive current (Ion) variation. In order to obtain robust design rules (i.e. keep-out zone) and spice model for TSV applications, electrical characteristics of CMOS devices were investigated in terms of distance between TSV and CMOS device in this work.

Comparison of Printed Circuit Board Property Variations in Response to Simulated Lead-Free Soldering

Use of lead-free solders such as Sn/Ag/Cu results in exposure of printed circuit boards to higher temperatures during assembly compared with eutectic tin-lead solder. If the thermo-mechanical and electrical properties of the laminate materials get affected by exposure to this higher temperature, that may impact the performance and reliability of the circuit board. Variations, if any, in laminate material properties before and after board assembly should be considered in the selection of appropriate laminates. The board and system designers need to be cognizant of such variations and account for them during laminate selection for an application. This paper presents guidelines for laminate selection along with the process used to derive the guidelines. The process includes measurement of key material properties (glass transition temperature, coefficient of thermal expansion, decomposition temperature, time-to-delamination, water absorption, flammability, dielectric constant, and dissipation factor), and their responses to lead-free soldering assembly conditions. A range of commercially available FR-4 printed circuit board laminate materials, classified on the basis of glass transition temperature (high, medium, and low), curing agents (dicyandiamide and phenolic), flame retardants (halogenated and halogen-free), and the presence of fillers, are included in the measurements. The measurements are conducted in accordance with IPC-TM-650 test methods before and after exposure to multiple lead-free soldering profiles. The extent of variations in the properties due to lead-free soldering exposures are reported and analyzed as a function of classification parameters. The causes behind the variations in material properties are investigated by Fourier transform infrared spectroscopy analysis and a conjunctional property analysis. This study also suggests that the preconditioning steps specified in the IPC test methods should address the initial moisture content of the laminate test samples in material property measurement tests, otherwise significant errors can be introduced.

Nonlinearities in thin-silicon die strength tests

While the semiconductor packages are evolving toward smaller package size and higher performance, the 3D IC or stacked-die packages are gaining popular. For these applications, IC wafers have to be ground to be relatively thin and the dies cut from these wafers have to possess sufficient strength against high stresses resulting from process handling, reliability testing, and operation. Hence, the strength of the dies, especially for the thin dies, has to be determined to ensure good reliability of the packages. Three-point bending test is widely used for measuring die strength; however the feasibility of the test is still questionable for determining strength of relatively thin dies. Meanwhile, the pin-on-elastic-foundation (PoEF) test [1] with special feature of bi-axial stress mode and elimination of the die edge effect has been proved more simple and reliable, but not for thin dies. In this study, the three-point bending test (under un-axial stress state) and the PoEF test (under bi-axial stress state) are evaluated for aiming at the thin-die strength determination which may features geometrical and contact nonlinearities. The feasibility of both test methods with their linear theories is evaluated by a nonlinear finite element method (NFEM) with taking into account geometrical and contact nonlinearities. The results show that these nonlinearities would cause an error of strength prediction by the linear beam theory for thin dies. For three-point bending test, the concept of moment equilibrium associated with the fitting equation for Fx extracted from the NFEM simulation is proposed and proved workable with good accuracy. The similar problem is faced in the PoEF test. The fitting equations based on the NFEM results are also proposed for calculating the strength of thin dies with better accuracy than theoretical formulation. Therefore, the nonlinearities has to be taken into account for both tests when the thin silicon dies are tested for strength.

Improved ball-on-elastic-pad and ball-on-hole tests for silicon die strength

For determining die strength, there are a couple of tests available in the literature, such as three-point and four-point bending, ball breaker, ball-on-the-ring, ring-on-the-ring, and recently proposed ball-on-elastic- pad (BoEP) and ball-on-the-hole (BoH) tests. Its well known that the test data reduction with theoretical formulations is more convenient and useful than that with numerical simulation results. However, those theoretical formulations have to be validated either by numerical simulation or experiments, before their applications. The objective of this study is to reevaluate and thus improve the existing BoEP and BoH tests for die strength using Hertzian contact theory, plate theories and finite element method (FEM). In this paper, the FEM analysis with “contact element” successfully has been verified with Hertzian contact theory and further proved that Hertzian contact theory can be employed to estimate the contact area for calculating die strength in both methods. The results indicate that the consistency between the theoretical formulation and FEM simulation for both tests exist only at the relatively large radius of ball and high applied loading, because the feasibility of the theoretical formulations requires large contact radius(> 0.06 mm) or area. For the BoEP test, the elastic moduli of elastic pad and ball have no obvious effect on the difference of maximum die stress between theoretical and FEM results. The theoretical solutions associated with contact radius determined by Hertzian contact theory are successfully proved for improving BoEP and BoH tests for die strength determination, and for better accuracy of die strength the ball with radius ranging from 2 mm to 4 mm is suggested.