P. S. Huang

Investigation on Cu TSV-Induced KOZ in Silicon Chips: Simulations and Experiments

The technology of through silicon via (TSV) is one of the most promising enablers for 3-D integrated circuit (IC) integration. The embedded TSVs in silicon chips would, however, cause the problem of carrier mobility changes in surrounding devices. There are two objectives in this paper. The first objective is to numerically and experimentally investigate the effect of via-middle Cu TSV on the mobility change of metal-oxide-semiconductor transistors in the wafer-level silicon chips for this 3-D IC integration. The second objective is to further determine the keep-out zone (KOZ) in terms of the key parameters such as the SiO2 layer effect, the zero-stress temperature, the single and array vias, the through and blind vias, silicon material properties, as well as the diameter and pitch of vias. KOZs based on the >10% change in carrier mobility are identified by finite element numerical calculations associated with the corresponding piezoresistance coefficients. The numerical results of the changes in saturated current are experimentally validated with good agreements. With the results of detailed analyzes using this validated model, the key parameters affecting the KOZs are presented and further discussed in detail.

An investigation into warpages, stresses and keep-out zone in 3D through-silicon-via DRAM packages

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moire are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.

A Study of Overlaying Dielectric Layer and Its Local Geometry Effects on TSV-Induced KOZ in 3-D IC

The aim of this paper is to investigate the effects of overlaying dielectric layer and its local geometry on keep-out zone (KOZ) induced from through-silicon via (TSV) in 3-D integrated circuit applications. Prior to the study, the saturated current changes (or corresponding carrier mobility changes) of both nMOS and pMOS transistors from the finite element simulations are validated with experimental data. After the model verification, six cases with various local dielectric structures are proposed to minimize KOZ. The results show that the case with an embedded SiO2 on the top of Cu TSV has the least effect on saturated current change (or the minimum KOZ) among those cases. Furthermore, the various embedded-SiO2 depths on the top of Cu TSV are further investigated. It is found that saturated current change of pMOS placed in both horizontal and vertical directions on Si substrate can be minimized using a 6-μm-deep embedded SiO2. Besides those results, the effects of other parameters such as the thickness of overlaying dielectric layer, shallow trench isolation, and silicon crystal orientations of [110] and [100] are also presented and discussed in this paper.

Warpage and curvature determination of PCB with DIMM socket during reflow process by strain gage measurement

The purpose of this study is to in-situ measure the warpage of the PCB with surface-mount dual in-line memory module (DIMM) sockets during reflow process by using strain gages. In the experiments, a full-field shadow moire is used for measuring real-time out-of-plane deformations (or warpage) of the PCB with DIMM sockets under heating condition. A finite element method (FEM) is used to analyze the thermally-induced deformation of the PCB with DIMM sockets in order to ensure the validity of the measurement. The conventional strain gages and rosette are employed to in-situ measure the strains (even though they are in-plane strain data) in this PCB specimen during the solder reflow process. The results indicate that the strain gage measurement can be used to determine the bending strains of the PCB occurring during the solder reflow. These bending strains can be transferred to curvature data and global warpage. Therefore, it provides a real-time and easy-to-use method for monitoring the PCB warpage under temperature variation during the reflow process. In addition, the strain gage rosette has been successfully proved to be an enabling measurement of the local and full-field deformation of the PCB with DIMM socket during reflow process.

The impact of through silicon via proximity on CMOS device

As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes stresses on silicon near the TSV, the impact of TSV proximity on CMOS must be evaluated at various operation temperatures. In this paper, Cu-filled TSVs were fabricated in “via middle” process. The TSVs-induced mechanical stresses causing carrier mobility change that result in drive current (Ion) variation. In order to obtain robust design rules (i.e. keep-out zone) and spice model for TSV applications, electrical characteristics of CMOS devices were investigated in terms of distance between TSV and CMOS device in this work.

Mechanical design and analysis of direct-plated-copper aluminum nitride substrates for enhancing thermal reliability

Abstract Direct-plated-copper (DPC) aluminum nitride (AlN) substrate with a high thermal conductivity can provide a good alternative to conventional aluminum oxide (Al2O3) substrate for better heat dissipation in the high-power module applications. However, the DPC AlN substrate suffers AlN crack initiating at the edge corner of Cu film during thermal cycling, due to the higher thermal expansion coefficient mismatch with copper material. This study is to resolve the AlN crack problem of DPC AlN substrate during thermal cycling and further to provide important parameters for mechanical design for ensuring good thermal reliability. Prior to the analysis, the out-of-plane deformation measurement of a Cu-AlN bi-material plate subject to the solder reflow heating and cooling is conducted for evaluating the material property of the plated Cu film and residual stresses induced from the manufacturing and solder reflow process. The results show the hysteresis and Bauschinger-like behaviors for the Cu-AlN plate during the solder-reflow heating and cooling. It is also found from the validated finite element simulation that the Cu-film wedge angle, length, and thickness significantly affect the maximum 1st principal stress of AlN during thermal cyclic loading, and the predicted failure mode and location based on the maximum 1st principal stress is consistent with experimental observation. The other factors, such as single-side and double-side Cu-film (sandwich-structure-alike) substrates, length difference of Cu films, and the nonlinear property of Cu film will be presented and discussed in detail as well.

Strength evaluation of thin 3D-TSV memory chips by pin-on-elastic-foundation test

The pin-on-elastic-foundation (PoEF) test associated with theoretical equations is used for the strength determination of 3D-TSV thin memory die. FEM simulation is also applied to evaluate the test results and further provides an insight into failure mechanics. The 50μm-thick memory chips with Cu TSVs are tested, and the results of the applied load versus deflections and maximum loads for front-side and back-side surface controlling failures are obtained. It is found that the maximum loads at back-side controlled failure are slightly larger than those at front-side controlled failure either for on-via or away-from-via loading. And the maximum loads for on-via loading are lower than those for away-from-via loading by 16% for front-side failure and 26% for back-side failure. Based on the failure mechanism, the TSV structures in the memory chips are found to be one of dominant factors (or the weakest spots) of die strength. The detailed loading stresses and TSV-induced residual silicon stresses are calculated and then discussed in terms of controlling factors of chip strength.

Nonlinearities in thin-silicon die strength tests

While the semiconductor packages are evolving toward smaller package size and higher performance, the 3D IC or stacked-die packages are gaining popular. For these applications, IC wafers have to be ground to be relatively thin and the dies cut from these wafers have to possess sufficient strength against high stresses resulting from process handling, reliability testing, and operation. Hence, the strength of the dies, especially for the thin dies, has to be determined to ensure good reliability of the packages. Three-point bending test is widely used for measuring die strength; however the feasibility of the test is still questionable for determining strength of relatively thin dies. Meanwhile, the pin-on-elastic-foundation (PoEF) test [1] with special feature of bi-axial stress mode and elimination of the die edge effect has been proved more simple and reliable, but not for thin dies. In this study, the three-point bending test (under un-axial stress state) and the PoEF test (under bi-axial stress state) are evaluated for aiming at the thin-die strength determination which may features geometrical and contact nonlinearities. The feasibility of both test methods with their linear theories is evaluated by a nonlinear finite element method (NFEM) with taking into account geometrical and contact nonlinearities. The results show that these nonlinearities would cause an error of strength prediction by the linear beam theory for thin dies. For three-point bending test, the concept of moment equilibrium associated with the fitting equation for Fx extracted from the NFEM simulation is proposed and proved workable with good accuracy. The similar problem is faced in the PoEF test. The fitting equations based on the NFEM results are also proposed for calculating the strength of thin dies with better accuracy than theoretical formulation. Therefore, the nonlinearities has to be taken into account for both tests when the thin silicon dies are tested for strength.

Mechanical strength of thin Cu-TSV memory dies used in 3D IC packaging

The mechanical strength of the thin dies especially with copper through-silicon via (Cu-TSV), has to be determined for ensuring good yield during manufacture handling and packaging. In this study, three test methods: a line-load on elastic-foundation (LoEF) test, a 3-point bending (3PB) test and a 4-point bending (4PB) test are used for the strength determination of Cu-TSV thin memory dies. The results of displacement (deflection) versus applied load of TSV memory die and corresponding failure loads are presented. The maximum mechanical failure stress, so called apparent strength, of memory dies is determined from experimental failure loads associated with finite element analysis. In addition, the actual strength of memory dies, by the superposition of mechanical stress and thermal residual stress, is applied to predict the failure initiation point of memory dies. It is found that actual strengths of memory dies (controlled by Cu-TSV) obtained from these three tests are consistent, but with only 60% of the die strength without Cu TSV.

Determination of TSV-induced KOZ in 3D-stacked DRAMs: Simulations and experiments

This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO2 layer effect, zero-stress temperature, single and array vias, through and blind vias, as well as diameter and pitch of vias. From the results of this study, the zero-stress temperature has been successfully determined from experimental data. The KOZs based on the more than 10% change in carrier mobility (or 5% saturated current changes) have been identified by finite element numerical calculations associated with related piezoresistive coefficients. Numerical results of saturated current changes have been validated by good comparisons with experimental data. Based on the detailed analyses using this validated model, the key parameters affecting the KOZs will be presented and discussed in detail.