Maaike M. Visser Taklo

Strong, high-yield and low-temperature thermocompression silicon wafer-level bonding with gold

A systematic variation of process parameters for wafer-level thermocompression bonding with gold is presented for the first time. The process was optimized for high bond strength and high bond yield. In addition, the impact of the process temperature was investigated. A bond strength of 10.7 ± 4.5 MPa and a bond yield of 89% was achieved when bonding a wafer pair at 298 °C applying 4 MPa pressure for 45 min. A total of ten wafer pairs were bonded in a custom-built bonding tool and tested to establish the optimal process parameters. The bonded interface was found to be strong and dense enough for MEMS applications. The bonds were characterized using pull tests, transmission electron microscopy (TEM) and energy dispersive x-ray spectroscopy (EDS). The TEM inspections indicated that it is possible to form hermetic seals by using the presented bonding method.

3D Integration technology: Status and application development

As predicted by the ITRS roadmap, semiconductor industry development dominated by shrinking transistor gate dimensions alone will not be able to overcome the performance and cost problems of future IC fabrication. Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. Several full 3D process flows have been demonstrated, however there are still no microelectronic products based on 3D TSV technologies in the market — except CMOS image sensors. 3D chip stacking of memory and logic devices without TSVs is already widely introduced in the market. Applying TSV technology for memory on logic will increase the performance of these advanced products and simultaneously shrink the form factor. In addition to the enabling of further improvement of transistor integration densities, 3D integration is a key technology for integration of heterogeneous technologies. Miniaturized MEMS/IC products represent a typical example for such heterogeneous systems demanding for smart system integration rather than extremely high transistor integration densities. The European 3D technology platform that has been established within the EC funded e-CUBES project is focusing on the requirements coming from heterogeneous systems. The selected 3D integration technologies are optimized concerning the availability of devices (packaged dies, bare dies or wafers) and the requirements of performance and form factor. There are specific technology requirements for the integration of MEMS/NEMS devices which differ from 3D integrated ICs (3D-IC). While 3D-ICs typically show a need for high interconnect densities and conductivities, TSV technologies for the integration of MEMS to ICs may result in lower electrical performance but have to fulfill other requirements, e. g. mechanical stability issues. 3D integration of multiple MEMS/IC stacks was successfully demonstrated for the fabrication of miniaturized sensor systems (e-CUBES), as for automotive, health & fitness and aeronautic applications.

Use of conductive adhesive for MEMS interconnection in ammunition fuze applications

A novel conductive adhesive is used to interconnect MEMS test structures with different pad sizes directly to a printed circuit board (PCB) in a medium caliber ammunition fuze. The fuze environment is very demanding, with a setback acceleration exceeding 60,000 g and a centripetal acceleration increasing radially with 9000 g/mm. The adhesive shows excellent mechanical and thermal properties. The mounted MEMS test structures perform well when subjected to rapid temperature cycling according to military-standard 883G method 1010.8 test condition B. The test structures pass 100 temperature cycles, followed by a firing test where the test structures are exposed to an acceleration of more than 60,000 g.

Characterization and Failure Analysis of 3D Integrated Systems using a novel plasma‐FIB system

Today 3D integration based on TSVs is a well accepted approach to further improve Integrated Circuits in terms of miniaturization, performance, power consumption and heterogeneous integration. However, 3D integration comes with the introduction of many new processes and materials that may affect behavior and reliability of the overall system. Therefore, there is a strong demand for physical characterization and failure analysis and more explicitly, also for tools and techniques that allow for easy chip access and navigation to the site of interest and that can provide physical information at the nanometer scale within a large field of view.In the framework of the European project JEMSIP‐3D, a novel plasma‐FIB platform has been developed and evaluated by the project partners. This new platform has been characterized in terms of mill rates, resolution and ion assisted CVD kinetics and effective methods have been developed to suppress the curtaining that may appear on X‐sections due to variations in materia...

Nanoparticle assembly and sintering towards all-copper flip chip interconnects

The current feed capability of typical flip chip electrical interconnects is constrained by the solder alloy, as it is more susceptible to electromigration than the copper used for the pads and wires. Hence, interconnects formed by copper only mitigate the electromigration risk and/or allow to increase the current limit of the all-copper interconnect. In this work, two methods to form all-copper flip chip interconnects at an annealing temperature of 250 °C are presented. The interconnects in the contact region between Cu pillars and Cu pads with a pitch down to 150 μm are formed by Cu nanoparticle self-assembly and sintering. In the first method, the entire gap between a Cu pillar chip and a substrate was filled with a Cu nano-suspension. The formation of capillary bridges during the evaporation of the dispersant directed the self-assembly of the nanoparticles towards the contact region between Cu pillars and Cu pad. In the second method, the Cu pillar chip was dipped into a film of the Cu nano-suspension, followed by a transfer, placement and release with a die bonder onto pads on a substrate. The annealing of the Cu nanoparticles is performed in both cases in a reducing formic acid atmosphere. The first method was more susceptible to the formation of shorts between pillars, whereas the second method resulted in electrical functional chip to substrate assemblies. Interconnects with a mean electrical resistance of 26 ± 3 mΩ and a shear strength ranging from 4.6 to 12.3 MPa were achieved. The sintered Cu nanoparticles bridged gaps up to 10 μm between copper pillars and pads, demonstrating the potential to apply the joint also on non-planar substrates. Nevertheless, imperfections such as voids and cracks are still present in the joints and need further process development, to improve the quality and process robustness further.

Impact of SiO2 on Al–Al thermocompression wafer bonding

Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO2 film had higher dicing yield and bond strength than the laminates without SiO2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon.

Reliable HT electronic packaging — Optimization of a Au-Sn SLID joint

Au-Sn solid-liquid-interdiffusion (SLID) bonding has proven to be a favorable die attach and interconnect technology for high temperature (HT) applications. In combination with silicon carbide (SiC) devices, Au-Sn SLID bonding has potential to be a key technology in future HT electronic systems. In this paper an optimized HT Au-Sn SLID joint is presented. Finite element analysis (FEA) were performed to design an optimized Au-Sn SLID joint for a HT Cu / Si3N4 / Cu / NiP / Au / Au-Sn / Au / Ni / Ni2Si / SiC package (representing a SiC transistor assembled onto a Si3N4 substrate). The optimized package (minimized residual stress at application temperature) was fabricated and investigated experimentally. The bond strength of the optimized joint was superb, with an average die shear strength of 140 MPa. An optimization of bonding time (1–10 min), temperature (290–350 °C) and atmosphere (ambient air, vacuum) was performed. Superb joints were fabricated at a bonding time of 6 min, and a bonding temperature of 300 °C, demonstrating an efficient, industry-feasible Au-Sn SLID bonding process.

Characterization of hermetic wafer-level Cu-Sn SLID bonding

A flux-less copper-tin (Cu-Sn) solid-liquid inter-diffusion (SLID) bonding process, providing a cost-effective hermetic vacuum sealing at wafer-level, has been investigated. Observations have been made indicating that the storage time of Cu-Sn plated wafers before bonding is critical with regard to voiding. Growth of the intermediately formed intermetallic compound (IMC), Cu6Sn5, was investigated as a possible cause. Room temperature aging of Cu-Sn plated wafers prior to bonding was performed as well as annealing of un-bonded Cu-Sn plated wafers. The presence of large Cu6Sn5 and Cu3Sn crystallites which nearly depleted the Sn was observed by optical microscopy after annealing. If large Cu6Sn5 grains from opposite contact planes meet at the bond interface, voids are predicted to be formed during the subsequent stages of liquid inter-diffusion and solidification. Implications on the Cu-Sn bonding strategy based on the results are presented.

Miniaturised Sensor Node for Tire Pressure Monitoring (e-CUBES)

Tire pressure monitoring systems (TPMS) are beneficial for the environment and road and passenger safety. Miniaturizing the TPMS allows sensing of additional parameters. This paper presents a miniaturized TPMS with a volume less than 1 cm3, realised by 3D stacking and through-silicon via (TSV) technology. Suitable technologies with low electrical resistance and high bond strengths were evaluated for stacking the microcontroller, transceiver, pressure sensor and bulk acoustic resonator (BAR) in the TPMS. 60 μm deep W-filled TSVs with resistance 0.45 Ω and SnAg micro bumps with a bond strength of 53 MPa were used for stacking the transceiver to the microcontroller. TSVs through the whole wafer thickness with resistance 6 Ω were used for the pressure sensor. Au stud bumps were used for stacking the pressure sensor and BAR devices. The final TPMS stack was packaged in a moulded interconnect device (MID) package.

Compliant interconnects for reduced cost of a ceramic ball grid array carrier

The transition to lead free solders has accentuated the inherent reliability problem in electronic packaging caused by thermo mechanical mismatch between different parts of an assembled system. To mitigate this problem, polymer core solder balls (PCSBs) have been proposed as a mechanically more flexible and therefore more reliable alternative to solid solder balls normally used for such applications. In this paper we report results from testing of PCSBs used for connecting and attaching a low temperature co-fired ceramic (LTCC) Ball Grid Array (BGA) carrier to an FR-4 board. The results appear to be strongly dependent on the assembly process. However, the results also indicate that with a properly executed assembly process, these balls represent an alternative to traditional solder balls with remarkable resistance to thermal cycling.