Nicolas Lietaer

3D Integration technology: Status and application development

As predicted by the ITRS roadmap, semiconductor industry development dominated by shrinking transistor gate dimensions alone will not be able to overcome the performance and cost problems of future IC fabrication. Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. Several full 3D process flows have been demonstrated, however there are still no microelectronic products based on 3D TSV technologies in the market — except CMOS image sensors. 3D chip stacking of memory and logic devices without TSVs is already widely introduced in the market. Applying TSV technology for memory on logic will increase the performance of these advanced products and simultaneously shrink the form factor. In addition to the enabling of further improvement of transistor integration densities, 3D integration is a key technology for integration of heterogeneous technologies. Miniaturized MEMS/IC products represent a typical example for such heterogeneous systems demanding for smart system integration rather than extremely high transistor integration densities. The European 3D technology platform that has been established within the EC funded e-CUBES project is focusing on the requirements coming from heterogeneous systems. The selected 3D integration technologies are optimized concerning the availability of devices (packaged dies, bare dies or wafers) and the requirements of performance and form factor. There are specific technology requirements for the integration of MEMS/NEMS devices which differ from 3D integrated ICs (3D-IC). While 3D-ICs typically show a need for high interconnect densities and conductivities, TSV technologies for the integration of MEMS to ICs may result in lower electrical performance but have to fulfill other requirements, e. g. mechanical stability issues. 3D integration of multiple MEMS/IC stacks was successfully demonstrated for the fabrication of miniaturized sensor systems (e-CUBES), as for automotive, health & fitness and aeronautic applications.

First fabrication of full 3D-detectors at SINTEF

3D-detectors, with electrodes penetrating through the entire substrates have drawn great interests for high energy physics and medical imaging applications. Since its introduction by C. Kenney et al in 1995, many laboratories have begun research on different 3D-detector structures to simplify and industrialise the fabrication process. SINTEF MiNaLab joined the 3D collaboration in 2006 and started the first 3D fabrication run in 2007. This is the first step in an effort to fabricate affordable 3D-detectors in small to medium size production volumes. The first run was fully completed in February 2008 and preliminary results are promising. Good p-n junction characteristics have been shown on selected devices at the chip level with a leakage current of less than 0.5 nA per pixel. Thus SINTEF is the second laboratory in the world after the Stanford Nanofabrication Facility that has succeeded in demonstrating full 3D-detectors with active edge. A full 3D-stacked detector system were formed by bump-bonding the detectors to the ATLAS readout electronics, and successful particle hit maps using an Am-241 source were recorded. Most modules, however, showed largely increased leakage currents after assembly, which is due to the active edge and p-spray acting as part of the total chip pn-junction and not as a depletion stop. This paper describes the first fabrication and the encountered processing issues. The preliminary measurements on both the individual detector chips and the integrated 3D-stacked modules are discussed. A new lot has now been started on p-type wafers, which offers a more robust configuration with the active edge acting as depletion stop instead of part of the pn-junction.

Development of cost-effective high-density through-wafer interconnects for 3D microsystems

High-density through-wafer interconnects are of great interest for fabricating real 3D microsystems. A complete solution for realizing through-wafer interconnects is presented. The proposed solution is believed to be cost effective and easy to integrate in a device process flow. A deep reactive ion etch process was developed to etch 20 x 20 μm 2 via holes through 300 μm thick silicon wafers. Thermal oxide is used to insulate the vias from the bulk silicon and heavily doped polysilicon is used as the conductor. Aluminum metallization is provided on both sides of the wafer. The electrical resistance of a single through-wafer via is close to 30 Ω.

Test beam results of 3D silicon pixel sensors for the ATLAS upgrade

Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS inner detector solenoid field. Sensors were bump-bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

Results from the first prototype of large 3D active edge sensors

3D active edge sensors have advantages such as radiation hardness and edgeless capability. With the use of deep reactive ion etching and wafer bonding, 18.5 by 20.5 mm2 3D detectors with active edges have been successfully fabricated at SINTEF MiNaLab. These sensors are compatible with the ATLAS FE-I4 readout electronics. Fabrication process and difficulties are presented and the preliminary electrical measurements are also discussed.

Miniaturised Sensor Node for Tire Pressure Monitoring (e-CUBES)

Tire pressure monitoring systems (TPMS) are beneficial for the environment and road and passenger safety. Miniaturizing the TPMS allows sensing of additional parameters. This paper presents a miniaturized TPMS with a volume less than 1 cm3, realised by 3D stacking and through-silicon via (TSV) technology. Suitable technologies with low electrical resistance and high bond strengths were evaluated for stacking the microcontroller, transceiver, pressure sensor and bulk acoustic resonator (BAR) in the TPMS. 60 μm deep W-filled TSVs with resistance 0.45 Ω and SnAg micro bumps with a bond strength of 53 MPa were used for stacking the transceiver to the microcontroller. TSVs through the whole wafer thickness with resistance 6 Ω were used for the pressure sensor. Au stud bumps were used for stacking the pressure sensor and BAR devices. The final TPMS stack was packaged in a moulded interconnect device (MID) package.

TSV development for miniaturized MEMS acceleration switch

Fragile micromachined MEMS structures are usually protected by bonding a capping wafer to the device wafer itself. As opposed to using lateral interconnects at the interface between the cap wafer and the device wafer, the use of vertical through silicon vias (TSVs) significantly simplifies the mounting of the components and it also results in the smallest footprint. This paper presents the concept chosen for fabricating a miniaturized MEMS acceleration switch with TSVs through the SOI (silicon on insulator) device wafer, as well as the experimental results of the TSV process development that was done for this particular application. Especially challenging was the development of an etching process that can etch the thick buried oxide of the SOI wafer through high aspect ratio trenches.

Electrical Characterization and Preliminary Beam Test Results of 3D Silicon CMS Pixel Detectors

The fabrication of 3D detectors which requires bulk micromachining of columnar electrodes has been realized with advancements in MEMS technology. Since the fabrication of the first 3D prototype in Stanford Nanofabrication Facility in 1997, a significant effort has been put forth to transfer the 3D detector technology to large scale manufacturing for future high luminosity collider experiments, in which the radiation hardness will be the primary concern, and other applications such as medical imaging and X-ray imaging for molecular biology. First, alternative 3D structures, single type column (STC) and double-side double type column (DDTC) 3D detectors, were produced at FBK-irst (Trento, Italy) and CNM-Barcelona (Spain), and assessed thoroughly to improve the production technology towards the standard full-3D detectors. The 3D collaboration has been extended to include SINTEF (Norway), which is committed to small to medium scale production of active edge full-3D silicon sensors. This paper focuses on p-type 3D detectors compatible with the CMS pixel front end electronics from the second run of fabrication at SINTEF clean room facilities. The sensors that passed the wafer level electrical characterization have been bump-bonded at IZM (Germany), assembled into modules and wire-bonded for functional characterization at Purdue University. We report the leakage current characteristics, bump-bond quality, threshold, noise, and gain measurement results of these 3D modules as well as the preliminary beam test data taken at Fermi National Accelerator Laboratory.

3D Integration of MEMS and IC: Design, Technology and Simulations

A 3D integrated silicon stack consisting of two MEMS devices and two IC devices is presented. The MEMS devices are a pressure sensor and a bulk acoustic resonator (BAR). The stack was constructed for a tire pressure monitoring system (TPMS) which was one out of three demonstrators for an EU funded project called e-CUBES. Thermal simulations were performed to check the level of thermo-mechanical stresses induced on the pressure sensor membrane during extreme environmental conditions. Additional simulations were made to calculate the exact temperature on the BAR device during operation as this was important for the operational frequency. This paper presents and discusses the technology choices made for the stacking of the pressure sensor and the BAR. Results are given from simulations, initial short-loop experiments and for the final stacking.

High aspect ratio deep RIE for novel 3D radiation sensors in high energy physics applications

3D detectors with electrodes penetrating through the entire silicon substrate have many advantages over conventional planar silicon technology, for example, high radiation tolerance. High aspect ratio through-wafer holes are essential in such fabrication, and deep reactive ion etching (DRIE) is used. A series of DRIE processes were tested and optimised to achieve the required aspect ratio, and in 5-¿m wide trenches, aspect ratios of 58:1 were achieved.