Maarten Cauwe

Broadband Material Parameter Characterization for Practical High-Speed Interconnects on Printed Circuit Board

Mainstream applications nowadays offer high-speed performance that until recently was only present in high-end applications. Special high-frequency materials and processing steps are, due to their inherent cost, not suited for high-volume applications. In this paper, a wideband material characterization technique to compare the behavior of different base materials is presented. The methodology can also be used for a quantitative analysis of the high-frequency limitations of traditional printed circuit board processing steps as thick copper plating and surface finish. It is based on the propagation constant extraction as part of the multiline through-reflect-line calibration. This powerful calibration technique makes it possible to directly compare different materials or processing steps, without the need for advanced modelling. From the extracted propagation constant, a more detailed analysis of the dielectric constant and the loss factor of the substrate material can be performed, based on known and tested formulas for microstrip transmission lines. Adaptations for a high track thickness to substrate height ratio and for the presence of a solder mask can be derived from the results. The practical material parameter extraction method proposed in this paper makes it possible for designers to overcome some of the high-frequency limitations associated with high-volume applications.

Industrial and technical aspects of chip embedding technology

Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded components, superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment of the chips, resulting in good reliability. At PCB manufacturing level, 50 mum thin chips have been embedded with pitches up to 200 mum in up to 18ldquotimes24rdquo panels. Embedding of chips at 100 mum pitch has been achieved at prototype level. Further developments of chip embedding can extend to even finer pitches without redistribution methods only with concurrent developments in ultra fine line patterning, plating methods and chemistries, assembly machines. New manufacturing processes should combine PCB processing and die assembly in one production line in order to benefit the most from this combination without the difficulties of transport between different manufacturing plants. Furthermore, new testing methodologies will be developed and a new supply chain will be created due to incorporation of embedding technologies to PCB production. This paper discusses in detail the technology and manufacturing challenges arisen from the integration of embedding technologies to PCB manufacturing processes.

Fabrication and Characterization of Flexible Ultrathin Chip Package Using Photosensitive Polyimide

Assembly of thinned die has become common practice to meet the demand for smaller and lighter electronic products. One way to achieve this goal is to embed the thinned die into two dielectric films, which results in a flexible ultrathin chip package (UTCP). This paper describes a new UTCP process flow with microvia formation by standard UV lithography through photosensitive polyimide (PSPI). Such microvia-formation method proved to be more reliable than laser drilling techniques and simpler than a dry etching process. Since the used PSPI is self-priming, a thin layer of potassium chloride was introduced as a release layer. In the end, the polyimide encapsulation of the thinned die can be released from the carrier substrate and becomes a flexible chip package with a total thickness of around 50 μm. Daisy-chain test dies were encapsulated inside spin-coated polyimide films. Excellent chip-to-package interconnection was demonstrated by electrical daisy chain and contact resistance measurements. Bending tests and thermal cycling tests were also performed on the daisy-chain test vehicles. Desired flexibility and reliability of UTCPs was observed.

Novel interconnect methodologies for ultra-thin chips on foils

Reliable interconnection technology is key to the realization of reliable hybrid microelectronic systems that combine printed electronics and silicon technology. Flexible hybrid electronic systems-in-foil (SiF) that are typically suited for roll-to-roll (R2R) manufacturing place additional requirements and demands on interconnects. In this paper, three novel interconnection methodologies for SiF are compared for a novel face-up integration approach for ultra-thin chip on foil. Laser scribing, inkjet printing and laser-induced forward transfer (LIFT) are the technologies compared with each other, as well as with electroplating, a standard technology widely used in the electronics industry. The comparison is based on experimental investigation into via filling, interconnect deposition, electrical conductivity and interconnect reliability. The selection of an interconnection technology for practical implementation is the key outcome of this paper.

Large area flexible lighting foils using distributed bare LED dies on polyester substrates

Integration of LEDs on flexible foil substrates is of interest for flexible lighting applications and for backlights for flexible displays. Such a large area lighting device can be made by integrating a matrix of closely spaced LEDs on a flexible foil substrate. Preferably, these LEDs are integrated unpackaged, i.e. as bare dies, as this reduces footprint, thickness and cost. As substrates, low cost materials like polyethylene terephthalate (PET) should preferably be used. However, the use of these materials also imposes limitations. Especially, their low thermal stability limits the maximum temperatures during the processing and the thermal dissipation of the LED during operation will pose constraints on the thermal design. This paper describes the results of research on possibilities for integrating bare die LEDs with such low cost flexible PET foils. Bonding of LED dies on PET substrates with copper circuitry using conductive adhesives was performed. Both anisotropic conducting adhesives and isotropic conducting adhesives were investigated. An experimental comparison is made between the different techniques based on temperature/humidity reliability and flexural stability of the bonded LEDs. Additionally, finite element (FE) thermal modeling results of adhesively bonded LED-on-foil configurations are presented. The role of the different materials and the effect of their geometries on the temperature distribution in the simulated devices are discussed. The results are compared to experimentally observed temperature distributions using infrared thermal imaging in LED on PET foil reference devices. Finally a demonstrator device of 64 LEDs on flexible copper-PET substrate is presented.

Laser ablation as an enabling technology for opto-boards

The use of optical interconnections for short distance interconnections requires the integration of optical layers and structures on printed circuit boards. The paper describes the use of laser ablation as a versatile technique for the fabrication of a wide variety of shucmes and as an enablmg technology for the fabrication of such opto-hoards. It is shown that waveguides, deflecting optics, coupling structures, alignment features and micro-optical elements can all be fabricated in a single process. These processing steps are compatible with the standard process flow of an FR4-based PCB.

Mechanical and electrical properties of ultra-thin chips and flexible electronics assemblies during bending

Ultra-thin chips of less than 20 μm become flexible, allowing integration of silicon IC technology with highly flexible electronics such as food packaging sensor systems or healthcare and sport monitoring tags as wearable patches or even directly in clothing textile. The ultra-thin chips in these products will be bent to a very high curvature, which puts a large strain on the chips during use. In this paper a modified four-point bending method is presented, which is capable of measuring chip stress at high curvatures. The strength of several types of ultra-thin chips is evaluated, including standalone ultra-thin test chips and back-thinned 20 μm thick microcontrollers, as well as assemblies containing integrated ultra-thin microcontroller chips. The effect of chip thickness, bending direction and backside finish on strength and minimum bending radius is investigated using the modified four point bending method. The effect of bonding ultra-thin chips to flexible foils on the assembly strength and minimum bending radius is evaluated as well as the effect of bending on electrical properties of the bonded microcontroller dies.

High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. Initially, thinned dies are embedded in a polyimide interposer with a fine-pitch metal fanout, resulting in ultrathin chip packages (UTCPs). Next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by the introduction of an additional layer of interposer, which makes it flat at the chip edge and thus the whole package is named as flat-UTCP. In addition to that, randomness in nonfunctional package positions per panel reduces the overall yield of the whole process up to a certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of four electrically erasable programmable read-only memory dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield.

Microwave heater at 20 GHz for nanoliter scale digital microfluidics

This paper proposes an optimized microwave heater at 20 GHz for nanoliter scale liquid samples in digital microfluidics. The developed measurement setup allows translating of the reflection coefficient of the heater to the temperature change of the water droplet via the temperature dependency of the liquid permittivity, thus avoiding a contact-based temperature measurement. Measurements have been carried out on pure water samples of 500 nL at power levels of 20 and 23 dBm at the probe tips. The measured data agrees very well with multiphysics simulation data. Heating performance has been characterized and high temperature gradients of 30 deg. C per second have been measured.

Sensitivity Analysis of Broadband On-Wafer Dielectric Spectroscopy of Yeast Cell Suspensions up to 110 GHz

This letter presents broadband on-wafer dielectric spectroscopy of bakers yeast cell suspensions up to 110 GHz. A detailed analysis of the sensitivities to measurement repeatability and uncertainties in the multi-step de-embedding procedure is performed. The Cole-Cole dispersion parameters of the cell suspensions are obtained from measured complex permittivity data between 0.5 and 110 GHz. Our analysis shows that the measured complex permittivity per frequency is most sensitive to length uncertainties of the test fixture, while the relaxation time in the Cole-Cole model is most sensitive to measurement repeatability.