Maarten Kuijk

Impact of texture-enhanced transmission on high-efficiency surface-textured light-emitting diodes

The transmission properties of semiconductor surfaces can be changed by surface texturing. We investigate these changes experimentally and find that an enhancement of the angle-averaged transmission by a factor of 2 can be achieved with optimum texturing parameters. This enhanced transmission provides an additional light extraction mechanism for high-efficiency surface-textured light-emitting diodes. External quantum efficiencies of 46% and 54% are demonstrated before and after encapsulation, respectively.

Calculation of the current response of the spatially modulated light CMOS detector

We present an analytical model that allows to calculate the current response of a spatially modulated light CMOS detector (SML-detector) and compare this response with the response of a traditional CMOS photodetector. It is shown that the SML detector already yields a three orders of magnitude faster response time than a traditional CMOS detector in a 0.25 /spl mu/m CMOS technology. This response time will further decrease as CMOS technology evolves. This analytical expression is compared with a numerical solution of the diffusion equation and with experimental results. Both show an excellent correspondence. Therefore we can conclude that the SML-detector is the solution of choice for cheap, CMOS-compatible receivers in integrated opto-electronic systems.

Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips

We present a first realization of a detector receiver combination based on the spatially modulated light detector (SML-detector). The SML-detector gives an output signal that has a shorter falling edge than that of a conventional CMOS detector. It is combined with a sense-amplifier in a standard 0.8-/spl mu/m CMOS technology, allowing one to receive over 155-Mb/s of light pulses at 5.6-/spl mu/W average light input power for /spl lambda/=860 nm. The detector 3-dB bit-rate is 300 Mb/s for this wavelength and for the used spatial topology. For /spl lambda/=635 nm the detector 3-dB bitrate is 510 Mb/s. Apart from monolithic integration of detector and receiver, further signal processing circuitry (including digital signal processing functions) can be integrated on the same chip. The compact system allows conceiving low cost densely packed optoelectronic receivers for parallel optical interconnects and for wavelength division multiplexing applications in the visible and the near-infrared wavelength range.

Large-signal-modulation of high-efficiency light-emitting diodes for optical communication

The dynamic behavior of high-efficiency light-emitting diodes (LEDs) is investigated theoretically and experimentally. A detailed theoretical description of the switch-on and switch-off transients of LEDs is derived. In the limit of small-signal modulation, the well-established exponential behavior is obtained. However, in the case of high injection, which is easily reached for thin active layer LEDs, the small-signal time constant is found to be up to a factor of two faster than the radiative recombination lifetime. Using such quantum-well LEDs, we have demonstrated optical data transfer with wide open eye diagrams at bit rates up to 2 Gbit/s. In addition, we have combined the use of thin active layers with the concept of surface-textured thin-film LEDs, which allow a significant improvement in the light extraction efficiency. With LEDs operating at 0.5 Gbit/s and 1 Gbit/s, we have achieved external quantum efficiencies of 36% and 29%, respectively.

A monolithic optoelectronic receiver in standard 0.7-μm CMOS operating at 180 MHz and 176-fJ light input energy

A novel monolithic optoelectronic receiver/converter system is presented in standard 0.7-/spl mu/m N-well CMOS technology. Differential light input incident on enlarged drains of two MOS transistors of a sense amplifier induces latching in either the digital HIGH state or the digital LOW state. The enlarged drains serve as photodiodes, circumventing hybridization techniques like flip-chip and/or solderbumping necessary when using III-V photodiodes. The first receivers of this type have photodetector areas of 15/spl times/15 /spl mu/m/sup 2/ and demonstrate bitrates of 180 Mb/s with a differential light input of 176 fJ. The electrical power dissipation is of the order of the dissipation of one CMOS logic gate. The very small total receiver area makes the receiver further perfectly suited for use in massive parallel optical interconnects between VLSI chips.

Fast turn‐off of two‐terminal double‐heterojunction optical thyristors

A double‐heterojunction optical thyristor is presented, that can be turned off in a few nanoseconds simply by using the anode to a negative voltage exceeding a certain threshold. Previously, nanosecond‐range turn‐off could only be achieved by carrier extraction via contacts to either or both of the center two thyristor layers. Our turn‐off method uses a PnpN layer structure for which punch‐through of the n‐layer under reverse bias of the P‐n diode can be reached before this diode breaks down. We thus achieve an improvement in turn‐off time by about 3 orders of magnitude over traditional two‐terminal thyristors.

Optoelectronic integrated receiver for inter-MCM and inter-chip optical interconnects

We present the integration of an ultra-sensitive III-V detector for digital optical signals with a novel comparator amplifier silicon circuit. The III-V detector is based on a differential pair of optical thyristors. It has at present a total area of 160/spl times/200 /spl mu/m/sup 2/, it operates at up to 155 Mbit/s and it requires optical inputs of 3 femtojoule at 830 nm. Its combination with the proposed silicon amplifier circuit results in a unique optoelectronic receiver ideally suited for inter-chip interconnects: it is extremely sensitive to input light, which allows to use less efficient yet reliable and cost-effective light sources (possibly LEDs); its speed is comparable to on-chip clock speed, appealing for inter-chip and inter-MCM interconnects; its low power dissipation and small size are features which permit massively parallel integration of the OEIR to achieve a huge aggregate bandwidth.

Demonstration of optoelectronic logic operations with differential pairs of optical thyristors

We show that differential pairs of pnpn optical thyristors can be used as optoelectronic logic elements. The logical operations AND, OR, NAND, and NOR are demonstrated and the functionality of the operation is reconfigured at the bit rate with the use of an additional optical bias bit. This opens the way to the development of fast and highly parallel optoelectronic information processing systems based on arrays of optical thyristors.

Image transcription between arrays of N-p-n-P optoelectronic switches

Double-heterojunction optical thyristors with a low holding current (0.2 mu A/6*10/sup -4/ cm/sup 2/) and a low breakover current (70 nA/6*10/sup -4/ cm/sup 2/) have been fabricated. Such thyristors can be made to switch when receiving an optical input signal from a twin device. Excellent uniformity and stability of the characteristics are obtained in arrays of such thyristors. Monolithic arrays of 25 thyristors connected in parallel have been processed. Winner-takes-all operation can be achieved in such arrays: when applying a bias to the array, only the one thyristor receiving maximum input light switches on, while all others are inhibited from reaching the on-state. With this system, the maximum of a light input pattern can be detected with a resolution of 0.3 nW-or 30 pJ for pulsed input light signals. Image transcription between thyristor arrays is demonstrated: the on-state of more than one thyristor can be copied with a single electrical pulse to the corresponding thyristors of a twin array. >

Experimental study of the spatially-modulated light detector

Abstract Usually, integrated detectors in CMOS exhibit long recovery times, limiting the detector bandwidth to only a few MHz. This is due to the long absorption length and the slow diffusion speed of photo-generated carriers. Different approaches have been proposed to solve these problems hereby taxing the compatibility with standard CMOS fabrication processing. We present a novel detector for high-speed light detection in standard CMOS. To solve the problem of slow CMOS-detector recovery, the incident light is spatially modulated and the spatially modulated component of the photo-generated carrier distribution is measured. Though only a single light input signal is required, from the detector on, analog signal processing can be achieved fully differentially. Subsequently, expected good PSRR (Power supply rejection ratio) allows integration with digital circuits. Avoiding hybridization eliminates the conventional problems caused by bonding-pad capacitance, bonding-wire inductance. This reduces the associated signal degradation. In addition, the very low detector capacitance, due to the low effectively used detector area and the low area capacitance of the n-well junction, yields high voltage readout of the detector. This facilitates further amplification and conversion to digital signal levels. The detector will be applicable in arrays due to expected low cross talk. The expected fields of operation involve: serial and parallel optical communication receivers (e.g. for WDM), DVD-reading heads with integrated amplifier, etc. First measurements show 200 Mbit/s operation with a detector-responsivity of 0.05 A/W at λ=860 nm and 0.132 A/W at λ=635 nm. The detector has inherently a low capacitance, in this case only 50 fF (for an effective detector area of 70×70 μm2).