P. Heremans

An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil

Forty years after the first silicon microprocessors, we demonstrate an 8-bit microprocessor made from plastic electronic technology directly on flexible plastic foil. The operation speed is today limited to 40 instructions per second. The power consumption is as low as 100 μW. The ALU-foil operates at a supply voltage of 10 V and back-gate voltage of 50 V. The microprocessor can execute user-defined programs: we demonstrate the execution of the multiplication of two 4-bit numbers and the calculation of the moving average of a string of incoming 6-bit numbers. To execute such dedicated tasks on the microprocessor, we create small plastic circuits that generate the sequences of appropriate instructions. The near transparency, mechanical flexibility, and low power consumption of the processor are attractive features for integration on everyday objects, where it could be programmed as, amongst other items, a calculator, timer, or game controller.

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature. >

Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications

When applying a high voltage to the floating gate of a split-gate transistor, enhanced hot-electron injection is observed that can be used for 5-V compatible EPROM or flash EEPROM device operation. The current collected on the gate is equal to the total electron injection current. Charge-pumping measurements and device simulations are used to analyze the electron injection and to determine its exact position in the transistor channel. Gate currents only show a weak dependence on both transistor channel lengths. The width of the spacer between both transistor gate has, however, been determined to be an important injection parameter. >

Unipolar Organic Transistor Circuits Made Robust by Dual-Gate Technology

Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin of zero- VGS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ~0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- VGS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.

Influence of transistor parameters on the noise margin of organic digital circuits

The concept of noise margin is crucial in the design and operation of digital logic circuits. Analytical expressions for the transfer curves of an inverter based on two depletion-mode p-type organic thin-film transistors (OTFTs) were calculated. Based on these expressions, the values for the noise margin of organic-based inverters were calculated. In this paper, the influence of the OTFT parameters on the noise margin is presented. Knowing that statistical variations of the transistor parameters are inherent to OTFT technology, these statistical variations are also taken into account. Finally, a circuit yield analysis is presented.

Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's

The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I/sub d/-V/sub g/ characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping. >

Low-voltage gallium–indium–zinc–oxide thin film transistors based logic circuits on thin plastic foil: Building blocks for radio frequency identification application

In this work a technology to fabricate low-voltage amorphous gallium-indium-zinc oxide thin film transistors (TFTs) based integrated circuits on 25 µm foils is presented. High performance TFTs were fabricated at low processing temperatures (<150 °C) with field effect mobility around 17 cm2 /V s. The technology is demonstrated with circuit building blocks relevant for radio frequency identification applications such as high-frequency functional code generators and efficient rectifiers. The integration level is about 300 transistors.

Mushroom microlenses: optimized microlenses by reflow of multiple layers of photoresist

A novel type of photoresist microlenses is conceived. The characteristic of these lenses is their mushroom shape: the lens dome is located at a certain controllable distance from the substrate, and the curvature of the lens is larger than that of traditional truncated-sphere lenses. These mushroom microlenses are equilibrium-state, stable products of reflow that are obtained when starting from a multilayer photoresist stack. Integration on light-emitting diodes results in enhanced output efficiency and directivity: a vertical-to-surface emission enhancement of up to a factor of 8 has been achieved.

On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D/sub it/-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior. >

Organic CuTCNQ integrated in complementary metal oxide semiconductor copper back end-of-line for nonvolatile memories

Nanowires of the organometallic semiconductor CuTCNQ were grown from TCNQ vapor in 250nm diameter vias of a Cu back end-of-line process. Corresponding prototypes of cross-point Cu∕CuTCNQ nanowire/Al memories exhibited nonvolatile bistable conductive switching for several ten write-erase cycles with switching currents below 10μA and current densities 1000 times higher than for large-area devices. Scaling of memory elements was also investigated.