Maciej J. Ciesielski

Wave-pipelining: a tutorial and research survey

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wave-pipelining and a survey of wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits.

BDS: a BDD-based logic optimization system

This paper describes a novel logic decomposition theory and a practical logic synthesis system, BDS. It is based on a new binary decision diagrams (BDD) decomposition technique which supports all types of decomposition structures, including AND, OR, XOR, and complex MUX, both algebraic and Boolean. As a result, the method is very efficient in synthesizing both AND/OR and XOR-intensive functions. It also has a capability to handle very large circuits, as it employs the BDD decomposition in the partitioned Boolean network environment. The experimental results show that BDD-based logic decomposition is a promising alternative to the existing logic optimization approaches. In particular, it offers a superior runtime advantage over traditional logic synthesis systems.

Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization

A novel theoretical formulation of the input encoding problem is presented, based on the concept of compatibility of dichotomies. The input encoding problem is shown to be equivalent to a two-level logic minimization. Three possible techniques to solve the encoding problem are discussed, based on: techniques borrowed from classical logic minimization (generation of prime dichotomies and solving the covering problem); graph coloring applied to the graph of incompatibility of dichotomies; and extraction of essential prime dichotomies followed by graph coloring. The extraction of essential prime dichotomies serves the same purpose as the extraction of essential prime implicants in logic minimization, in the sense that it reduces the size of the covering/graph coloring problem. The conditions of optimality of the solutions to the input encoding problem are discussed. For near-optimum results a powerful heuristic, based on an iterative improvement technique, has been developed and implemented as a computer program: dichotomy-based symbolic input encoding technique (DIET). The test results indicate the DIET compares favorably with KISS and NOVA in terms of the CPU time, is superior to both programs in terms of the encoding length, and requires considerably less memory. This method can be applied to the input encoding of combinational logic and the state assignment of finite state machines (FSMs) in both two-level and multilevel implementations. >

LPSAT: a unified approach to RTL satisfiability

LPSAT is an LP-based comprehensive infrastructure designed to solve the satisfiability (SAT) problem for complex RTL designs containing both word-level arithmetic operators and bit-level Boolean logic. The presented technique uses a mixed integer linear program to model the constraints corresponding to both domains of the design. Our technique renders the constraint propagation between the two domains implicit to the MILP solver thus enhancing the overall efficiency of the SAT framework. The experimental results are quite promising when compared with generic CNF-based and BDD-based SAT algorithms.

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

A Taylor expansion diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated

PLADE: a two-stage PLA decomposition

An efficient method for PLA decomposition, in which a single two-level Boolean function (PLA) is decomposed into two stages of cascaded PLAs such that the total area of all PLAs is smaller than that of the original PLA, is presented. The first stage may contain an arbitrary number of PLAs (generalized decoders), and the second stage contains a single PLA. Primary inputs are partitioned into disjoint sets of input variables and represented as multiple-valued variables so as to minimize the total PLA area. Two efficient algorithms for assignment of input variables to individual decoders are presented, one based on an integer programming technique and the other on graph partitioning. The constrained input encoding of the second-stage PLA is performed by an efficient procedure based on graph coloring and partitioning theory. >

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

This paper presents a new, compact, canonical graph-based representation, called Taylor expansion diagrams (TEDs). It is based on a general non-binary decomposition principle using Taylor series expansion. It can be exploited to facilitate the verification of high-level (RTL) design descriptions. We present the theory behind TEDs, comment upon its canonicity property and demonstrate that the representation has linear space complexity. Its application to equivalence checking of high-level design descriptions is discussed.

BDD decomposition for efficient logic synthesis

A unified logic optimization method efficient at handling both AND/OR-intensive and XOR-intensive functions is proposed. The method is based on iterative BDD decomposition using various dominators. Detail analysis of decomposable BDD structures leading to AND/OR, XOR and MUX decompositions are presented. Experiment shows that our synthesis results for AND/OR-intensive functions are comparable to those of SIS, and results for XOR-intensive functions are comparable to those of techniques targetting specifically XOR decomposition.

Clock period minimization with wave pipelining

A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arrivals at these elements. Constraints that relate the logic path delays from pairs of input flip-flops are derived. These constraints, in addition to known constraints relating input and output flip-flops, prevent destructive logic signal propagation interference. It is shown that in circuits without feedback the clock period reduction is limited by the shortest paths in the logic and the required signal separation between signals of distinct cycles. Application of this technique to logic with feedback is discussed. >

Functional Test Generation using Constraint Logic Programming

Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vectors, guided by miscellaneous coverage metrics to satisfy the simulation target, can be posed as a satisfiability problem (SAT). This paper presents a novel approach to solving SAT based on Constraint Logic Programming technique. The proposed SAT solver allows efficiently handling the designs with mixed word-level arithmetic operators and Boolean logic. It is applicable for designs specified at different levels, including HDL, RTL, and Boolean. The experimental results are quite encouraging compared with classical CNF-based, BDD-based, and LP-based SAT solvers.