Maciej Kopczynski

FPGA in Rough Set Based Core and Reduct Computation

In this paper we propose a combination of capabilities of the FPGA based device and PC computer for data processing using rough set methods. Presented architecture has been tested on a random data. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough sets operations in comparison to software implementation.

The First Step Toward Processor for Rough Set Methods

In this paper we propose a combination of capabilities of the FPGA based device and PC computer for data processing using rough set methods. Presented architecture has been tested on the exemplary data sets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

Generating Core in Rough Set Theory: Design and Implementation on FPGA

In this paper we propose the FPGA based device for data processing using rough set methods. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting core generation in comparison to software implementation.

Hardware Implementations of Rough Set Methods in Programmable Logic Devices

This paper describes current achievements in hardware realization of rough sets algorithms in FPGA (Field Programmable Gate Array) logic devices. At the moment, only few ideas and hardware implementations have been created. This chapter is a survey of them.

FPGA in Rough-Granular Computing: Reduct Generation

In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation.

Rough Sets Based LEM2 Rules Generation Supported by FPGA

In this paper we propose a combination of capabilities of the FPGA based device and PC computer for rough sets based data processing resulting in generating decision rules. Presented architecture has been tested on the exemplary datasets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

Hardware Supported Rough Sets Based Rules Generation for Big Datasets

In this paper we propose a combination of capabilities of the Field Programmable Gate Arrays based device and PC computer for rough sets based data processing resulting in generation of decision rules. Solution is focused on big datasets. Presented architecture has been tested in programmable unit on real datasets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

Core for Large Datasets: Rough Sets on FPGA

In this paper we propose the FPGA and softcore CPU based device for large datasets core calculation using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solution inside FPGA. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

Computation of Cores in Big Datasets: An FPGA Approach

In this paper we propose the FPGA and softcore CPU supported device for performing core calculation for large datasets using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solution inside FPGA. Sizes of the datasets were in range 1 000 to 10 000 000 objects. Results show the big acceleration in terms of the computation time using hardware supporting core generation unit.

Hardware Supported Rule-Based Classification on Big Datasets

In this paper we propose a combination of capabilities of the Field Programmable Gate Arrays based device and PC computer for data processing resulting in classification using previously generated decision rules. Solution is focused on big datasets. Presented architecture has been tested in programmable unit on real datasets. Obtained results confirm the significant acceleration of the computation time using hardware supported operations in comparison to software implementation.