Tomasz Grzes

FSM State Assignment Methods for Low-Power Design

In this paper we deal with the problem of the finite states machines (FSM) state assignment. CMOS- based digital circuits dissipate a power only during a transition at the output. Therefore one of the methods of the power minimization is to reassign the FSM states. We discuss the methods such as column-based and annealing-based as well as propose the new method called sequential method. Experimental results showed that the proposed method is approximately 10% better than the other discussed algorithms.

The First Step Toward Processor for Rough Set Methods

In this paper we propose a combination of capabilities of the FPGA based device and PC computer for data processing using rough set methods. Presented architecture has been tested on the exemplary data sets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

Generating Core in Rough Set Theory: Design and Implementation on FPGA

In this paper we propose the FPGA based device for data processing using rough set methods. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting core generation in comparison to software implementation.

FPGA in Rough-Granular Computing: Reduct Generation

In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation.

Hardware Supported Rough Sets Based Rules Generation for Big Datasets

In this paper we propose a combination of capabilities of the Field Programmable Gate Arrays based device and PC computer for rough sets based data processing resulting in generation of decision rules. Solution is focused on big datasets. Presented architecture has been tested in programmable unit on real datasets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

Computation of Cores in Big Datasets: An FPGA Approach

In this paper we propose the FPGA and softcore CPU supported device for performing core calculation for large datasets using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solution inside FPGA. Sizes of the datasets were in range 1 000 to 10 000 000 objects. Results show the big acceleration in terms of the computation time using hardware supporting core generation unit.

High-Speed Finite State Machine Design by State Splitting

A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The method can be easily included in designing the flow of digital systems in FPGA. The experimental results showed a high efficiency of the offered method. FSM performance increased by 1.73 times. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.

Hardware Supported Rule-Based Classification on Big Datasets

In this paper we propose a combination of capabilities of the Field Programmable Gate Arrays based device and PC computer for data processing resulting in classification using previously generated decision rules. Solution is focused on big datasets. Presented architecture has been tested in programmable unit on real datasets. Obtained results confirm the significant acceleration of the computation time using hardware supported operations in comparison to software implementation.

Maximal Discernibility Discretization of Attributes—A FPGA Approach

In this paper we propose the design for hardware cuts generating module for FPGA. Calculations are supported by softcore CPU. Presented architecture has been simulated and tested in VHDL IDE on real data. Implemented algorithm uses Maximal Discernibility (MD) approach. Results show the big acceleration of the computation time using hardware supporting discretization in comparison to pure software implementation.