Maciej Wielgosz

FPGA Architecture for Kriging Image Interpolation

This paper proposes an ultrafast scalable embedded image compression scheme based on discrete cosine transform. It is designed for general network architecture that guarantees maximum end-to-end delay (EED), in particular the Distributed Multimedia Plays (DMP) architecture. DMP is designed to enable people to perform delay-sensitive real-time collaboration from remote places via their own collaboration space (CS). It requires much lower EED to achieve good synchronization than that in existing teleconference systems. A DMP node can drop packets from networked CSs intelligently to guarantee its local delay and degrade visual quality gracefully. The transmitter classifies visual information in an input image into priority ranks. Included in the bitstream as side information, the ranks enable intelligent packet dropping. The receiver reconstructs the image from the remaining packets. Four priority ranks for dropping are provided. Our promising results reveal that, with the proposed compression technique, maximum EED can be guaranteed with graceful degradation of image quality. The given parallel designs for its hardware implementation in FPGA shows its technical feasibility as a module in the DMP architecture.

AN FPGA-BASED PLATFORM FOR A NETWORK ARCHITECTURE WITH DELAY GUARANTEE

The background that underlies this work is the envisioned real-time tele-immersive collaboration system for the future that supports delay-sensitive applications involving participants from remote places via their collaboration spaces (CSs). The end-to-end delay as high as 20 ms is required for good synchronization of such applications, for example collaborative dancing and remote conducting of choir. It is much lower than that facilitated by existing teleconference systems. A novel network architecture with delay guarantee, namely Distributed Multimedia Plays (DMP), has been proposed and designed to realize the vision. The maximum low latency is guaranteed because DMP network nodes can drop DMP packets of multimedia data from the CSs due to instantaneous traffic condition. Besides ultrafast processing time, modularity, and scalability must be taken into account in hardware design and implementation of the nodes for seamless incorporation of the modules. These lead us to employing field-programmable gate array (FPGA) due to its substantial computational power and flexibility. This paper presents an FPGA-based platform for the design and implementation of DMP network nodes. It provides a detailed introduction to the platform architecture and the simulation-implementation environment for the design. The modularity of the implemented node is shown by addressing three important modules for packet dropping, 3D warping, and image transform. Our compact implementation of the network node on Xilinx Virtex-6 ML605 mostly consumes very small amount of available resources. Moreover the elementary operations on our implementation takes (much) less than 5 μs as desired to meet the low-latency requirement.

FPGA-Based Platform for Real-Time Internet

Field-programmable gate arrays (FPGAs) are widely used in telecommunication due their substantial computational power and flexibly designed architecture. These features become especially important for applications of low transmission latency such as those supported by Distributed Multimedia Plays (DMP) architecture. Thus FPGAs are chosen in this work as the core building block of the system. Complex multi-node telecommunication systems require special design methodology contrary to small ICT applications usually implemented in HDL. The methodology should be based on the appropriate tools from FPGA vendors for support and maintenance. This paper presents an architecture of a module to be embedded in all the FPGA-based nodes constituting a platform for the Real Time Internet based on DMP. It is designed using an embedded development kit natively supported by Xilinx and flexible in available cores. We present the implementation results of the network-node module and the description of PCIe-based protocol for inter-FPGA communication.

FPGA implementation of the procedures for video quality assessment.

Video resolutions used in variety of media are constantly rising. While manufacturers struggle to perfect their screens it is also important to ensure high quality of displayed image. Overall quality can be measured using Mean Opinion Score (MOS). Video quality can be affected by miscellaneous artifacts, appearing at every stage of video creation and transmission. In this paper, we present a solution to calculate four distinct video quality metrics that can be applied to a real time video quality assessment system. Our assessment module is capable of processing 8K resolution in real time set at the level of 30 frames per second. Throughput of 2.19 GB/s surpasses performance of pure software solutions. To concentrate on architectural optimization, the module was created using high level language.

OpenCL-accelerated object classification in video streams using Spatial Pooler of Hierarchical Temporal Memory

The paper presents a method to classify objects in video streams using a brain-inspired Hierarchical Temporal Memory (HTM) algorithm. Object classification is a challeng-ing task where humans still significantly outperform machine learning algorithms due to their unique capabilities. A system which achieves very promising performance in terms of recogni-tion accuracy have been implemented. Unfortunately, conducting more advanced experiments is very computationally demanding; some of the trials run on a standard CPU may take as long as several days for 960x540 video streams frames. Therefore, authors decided to accelerate selected parts of the system using OpenCL. In particular, authors seek to determine to what extent porting selected and computationally demanding parts of a core may speed up calculations. The classification accuracy of the system was examined through a series of experiments and the performance was given in terms of F1 score as a function of the number of columns, synapses, min overlap and winners set size. The system achieves the highest F1 score of 0.95 and 0.91 for min overlap=4 and 256 synapses, respectively. Authors have also conduced a series of experiments with different hardware setups and measured CPU/GPU acceleration. The best kernel speed-up of 632x and 207x was reached for 256 synapses and 1024 columns. However, overall acceleration including transfer time was significantly lower and amounted to 6.5x and 3.2x for the same setup.

Ultrafast Scalable Embedded DCT Image Coding for Tele-immersive Delay-Sensitive Collaboration

A delay-sensitive, real-time, tele-immersive collaboration for the future requires much lower end-to-end delay (EED) for good synchronization than that for existing teleconference systems. Hence, the maximum EED must be guaranteed, and the visual-quality degradation must be graceful. Distributed Multimedia Plays (DMP) architecture addresses the envisioned collaboration and the challenges. We propose a DCT-based, embedded, ultrafast, quality scalable image-compression scheme for the collaboration on the DMP architecture. A parallel FPGA implementation is also designed to show the technical feasibility.