Madhavi G. Valluri

Runtime identification of microprocessor energy saving opportunities

High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the solution of these problems by presenting: linear regression models for power consumption and a detailed study of energy efficiency in a modern out-of-order superscalar microprocessor. These simple (2-input) yet accurate (2.6% error) models provide a valuable tool for identifying opportunities to apply power saving techniques such as clock throttling and dynamic voltage scaling (DVS). Also, future work in improving energy efficiency is motivated by a detailed analysis of SPEC CPU 2000 workloads. The vast majority of workloads are found to yield very low energy efficiency due to the frequency of level two (L2) cache misses and misspeculated instructions.

Speeding up STL Set/Map Usage in C++ Applications

In this work we augment the red-black tree implementation of STL set /map with a doubly linked list that is in sorted order. This is done for the purpose of speeding up C++ applications that use set /map ::iterator considerably. In such cases, the doubly linked list helps in iterating over the set /map quickly. Usually the ++/--- operations have an amortized cost of O(1) for a red-black tree implementation. The linked list augmentation helps in improving the ++/--- operations to ?(1). In addition, our experiments for IBMs P5+ and P6 processors show that this mechanism improves performance for two SPEC CPU2006 benchmarks and there is no adverse cache effect when we support two additional pointers per node of a red-black tree.

Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors

This paper develops a technique that uniquely combines the advantages of compile-time static scheduling and hardware dynamic scheduling to reduce energy consumption in dynamically scheduled processors. In this hybrid-scheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time bypass the dynamic scheduling hardware and execute in a low-power static mode. Experiments on several media and scientific benchmarks demonstrate that the proposed scheme can provide significant reduction in energy consumption with negligible performance degradation