Satish Kumar Sadasivam

Test Generation Approach for Post-Silicon Validation of High End Microprocessor

Post-Silicon Validation faces numerous challenges in the areas of test generation efficiency, time utilization and comprehensive coverage of the various functionalities of advanced microprocessors. The proposed approach uses the concept of building a Master Test Program that is used to build multiple test-streams by utilizing an instruction pool and a data pool. It utilizes lightweight modules such as the Instruction Classifier and Organizer and the Data Pool Generator that generate test streams on the fly. A key advantage of this is that it extends coverage of the processor state space while reducing the build time greatly.

Power Aware Meta Scheduler for Adaptive VM Provisioning in IaaS Cloud

Cloud Computing provides on-demand access to a shared pool of configurable computing resources. The major issue lies in managing extremely large agile data centers which are generally over provisioned to handle unexpected workload surges. This paper focuses on green computing by introducing Power-Aware Meta Scheduler, which provides right fit infrastructure for launching virtual machines onto host. The major challenge of the scheduler is to make a wise decision in transitioning state of the processor cores by exploiting various power saving states inherent in the recent microprocessor technology. This is done by dynamically predicting the utilization of the cloud data center. The authors have extended existing cloudsim toolkit to model power aware resource provisioning, which includes generation of dynamic workload patterns, workload prediction and adaptive provisioning, dynamic lifecycle management of random workload, and implementation of power aware allocation policies and chip aware VM scheduler. The experimental results show that the appropriate usage of different power saving states guarantees significant energy conservation in handling stochastic nature of workload without compromising the performance, both when the data center is in low as well as moderate utilization.

IBM Power9 Processor Architecture

The IBM Power9 processor has an enhanced core and chip architecture that provides superior thread performance and higher throughput. The core and chip architectures are optimized for emerging workloads to support the needs of next-generation computing. Multiple variants of silicon target the scale-out and scale-up markets. With a new core microarchitecture design, along with an innovative I/O fabric to support several accelerated computing requirements, the Power9 processor meets the diverse computing needs of the cognitive era and provides a platform for accelerated computing.

Performance evaluation of Data Mining algorithms on three generations of Intel ® microarchitecture

Data Mining algorithms and machine learning techniques form a key part of the majority of computing applications today. They are becoming an inherent part of business decision processes, e-commerce, social networking and social media applications as well as commercial and scientific computing applications. It is becoming increasingly important to provide a high performance computing platform for these emerging data mining applications. In this paper we explore the performance characteristics of the data mining benchmark suite MineBench across three “tock” generations of Intel microarchitecture. Our objective is to study the impact of microarchitecture improvements on the performance of data mining algorithms. We present comparative microarchitecture characteristics between data mining algorithms and SPEC INT 2006 benchmarks. We have proposed a generic cycle accounting methodology to attribute performance improvements to various units of the microprocessor. The proposed methodology helps differentiate the impact on performance due to front-end and back-end microarchitecture improvements.

Comparative performance study of SPEC INT 2006 benchmarks on nehalem, sandybridge and haswell microarchitectures

Microarchitecture enhancements are incorporated in each generation of across multiple units of the microprocessor. It is important to understand the impact of microarchitecture enhancements on workload performance. The internal organization of the modern superscalar out-of-order microprocessor is partitioned into two key sections - the front-end and the back-end. The front-end fetches, decodes and dispatches the instructions, and the back-end fetches the required data and executes the instructions. In this paper we have studied three generations of Intel (tock) microarchitecture improvements for SPEC INT 2006 workloads and categorized the improvements to both front-end and back-end optimizations using a cycle-based accounting methodology. We have also presented a high level instruction mix and generic microarchitecture characteristics across these three platforms.

Bandwidth-Aware Resource Optimization for SMT Processors

In this paper we have studied the memory bandwidth and throughput behaviour of various SPEC CPU2006 workloads in Single Threaded (ST) and Simultaneous Multi-threaded (SMT) environment with varying number of workload copies on IBM POWER7 processor. Our study reveals that for a number of workloads, the bandwidth gets saturated beyond a certain number of copies and the performance gain achieved by increasing the number of copies is very minimal after the bandwidth saturation point. The results also show that for such workloads, after bandwidth saturation, the similar performance as achieved with ST mode, can be achieved by moving the copies to SMT environment with reduced number of cores. This enables us to free-up cores which can be used to intelligently co-schedule non-memory intensive applications. This is of particular value in the HPC cloud environments and can help increase overall throughput of a cloud data-center or cluster. In a non-cloud or traditional environment, this approach has applicability in bringing out workload consolidation and better performance-per-watt. We have also demonstrated by actual hardware implementation of how the freed-up cores by moving to SMT can used effectively for doing other useful computations.