Madhumitra Sharma

Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches

Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Mechanism for optimizing generation of commit-signals in a distributed shared-memory system

Employing multiple channels for deadlock avoidance in a cache coherency protocol

Mechanism for reducing latency of memory barrier operations on a multiprocessor system

Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies

Low occupancy protocol for managing concurrent transactions with dependencies

Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor

Shadow commands to optimize sequencing of requests in a switch-based multi-processor system

Cache coherency mechanism using arbitration masks