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Dive into the research topics where Stephen R. Van Doren is active.

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Featured researches published by Stephen R. Van Doren.


architectural support for programming languages and operating systems | 2000

Architecture and design of AlphaServer GS320

Kourosh Gharachorloo; Madhu Sharma; Simon C. Steely; Stephen R. Van Doren

This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer GS320 architecture is specifically targeted at medium-scale multiprocessing with 32 to 64 processors. Each node in the design consists of four Alpha 21264 processors, up to 32GB of coherent memory, and an aggressive IO subsystem. The current implementation supports up to 8 such nodes for a total of 32 processors. While snoopy-based designs have been stretched to medium-scale multiprocessors by some vendors, providing sufficient snoop bandwidth remains a major challenge especially in systems with aggressive processors. At the same time, directory protocols targeted at larger scale designs lead to a number of inherent inefficiencies relative to snoopy designs. A key goal of the AlphaServer GS320 architecture has been to achieve the best-of-both-worlds, partly by exploiting the bounded scale of the target systems.This paper focuses on the unique design features used in the AlphaServer GS320 to efficiently implement coherence and consistency. The guiding principle for our directory-based protocol is to address correctness issues related to rare protocol races without burdening the common transaction flows. Our protocol exhibits lower occupancy and lower message counts compared to previous designs, and provides more efficient handling of 3-hop transactions. Furthermore, our design naturally lends itself to elegant solutions for deadlock, livelock, starvation, and fairness. The AlphaServer GS320 architecture also incorporates a couple of innovative techniques that extend previous approaches for efficiently implementing memory consistency models. These techniques allow us to generate commit events (which are used for ordering purposes) well in advance of formulating the reply to a transaction. Furthermore, the separation of the commit event allows time-critical replies to bypass inbound requests without violating ordering properties. Even though our design specifically targets medium-scale servers, many of the same techniques can be applied to larger-scale directory-based and smaller-scale snoopy-based designs. Finally, we evaluate the performance impact of some of the above optimizations and present a few competitive benchmark results.


Archive | 1997

Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches

Madhumitra Sharma; Simon C. Steely; Kourosh Gharachorloo; Stephen R. Van Doren


Archive | 1997

Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Madhumitra Sharma; Stephen R. Van Doren; Kourosh Gharachorloo; Simon C. Steely


Archive | 1997

Mechanism for optimizing generation of commit-signals in a distributed shared-memory system

Stephen R. Van Doren; Simon C. Steely; Kourosh Gharachorloo; Madhumitra Sharma


Archive | 1997

Mechanism for reducing latency of memory barrier operations on a multiprocessor system

Simon C. Steely; Madhumitra Sharma; Kourosh Gharachorloo; Stephen R. Van Doren


Archive | 2002

Mechanism for resolving ambiguous invalidates in a computer system

Stephen R. Van Doren; Gregory Edward Tierney


Archive | 1997

Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor

Madhumitra Sharma; Chester W. Pawlowski; Kourosh Gharachorloo; Stephen R. Van Doren; Simon C. Steely


Archive | 2002

Method and apparatus for implementing a relaxed ordering model in a computer system

Gregory Edward Tierney; Thomas J. Gibney; Stephen R. Van Doren


Archive | 2001

Cache coherency mechanism using arbitration masks

Simon C. Steely; Stephen R. Van Doren; Madhumitra Sharma


Archive | 1998

Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches

Simon C. Steely; Madhumitra Sharma; Stephen R. Van Doren; Kourosh Gharachorloo

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