Magnus Hansen

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. (Less)

A digital front-end and readout microsystem for calorimetry at LHC

Abstract A digital solution to the front-end electronics for calorimetric detectors at future supercolliders is presented. The solution is based on high speed A D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also being considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid, is used. This solution allows a new level of integration of complex analogue and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. It also allows a high degree of programmability at both the function and the system level, and offers the possibility of customising the microsystem with detector-specific functions.

A digital front-end readout microsystem for calorimetry at LHC-The FERMI project

The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high-speed analog-to-digital converters, a fully programmable pipeline/digital filter chain, and local intelligence. Questions of error correction, fault-tolerance, and system redundancy are also considered. A system integration of a multichannel device in a multichip, silicon-on-silicon microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions. >

Optimized digital feature extraction in the FERMI microsystem

Abstract We describe the digital filter section of the FERMI readout microsystem. The filter section, consisting of two separate filter blocks, extracts the pulse amplitude and time information for the first-level trigger process and performs a highly accurate energy measurement for higher-level triggering and data readout purposes. An FIR-order statistic hybrid filter structure is used to improve the amplitude extraction performance. Using a training procedure the filters are optimized to produce a precise and accurate output in the presence of electronics and pile-up noise, sample timing jitter and the superposition of high-energy pulses. As the FERMI system resides inside the detector where accessibility is limited, the filter implementations are presented together with fault tolerance considerations. The filter section is modelled with the VHDL hardware descriptive language and the subsystems are further optimized to minimize the system latency and circuit area.

The CMS Timing and Control Distribution System

The Compact Muon Solenoid (CMS) experiment operating at the CERN (European Laboratory for Nuclear Physics) Large Hadron Collider (LHC) is in the process of upgrading several of its detector systems. Adding more individual detector components brings the need to test and commission those components separately from existing ones so as not to compromise physics data-taking. The CMS Trigger, Timing and Control (TTC) system had reached its limits in terms of the number of separate elements (partitions) that could be supported. A new Timing and Control Distribution System (TCDS) has been designed, built and commissioned in order to overcome this limit. It also brings additional functionality to facilitate parallel commissioning of new detector elements. The new TCDS system and its components will be described and results from the first operational experience with the TCDS in CMS will be shown.

System level policies for fault tolerance issues in the FERMI project

The FERMI system, performing acquisition and DSP of calorimeter data in high energy collision experiments, planned at the LHC collider (CERN, Geneva, CH) is briefly overviewed. The system relies mainly upon the FERMI module, a dedicated VLSI multichip device performing most of the above functions, which is to be installed in large quantities (around 10/sup 5/) in the immediate neighborhood of the collider itself, requiring rad-hard features. The issues for a system which absolutely requires fault diagnosis and possibly fault tolerance are described, with regard to the FERMI module itself.

A Digital Front-end Readout Mlcrosystem For Calorimeters At LHC

The Front-End Read-out MIcrosystem (FERMI) for calorimeters at LHC presented last year has been further developed with the aim to achieve a full silicon implementation early 1994. Each microsystem will, as before, contain 9 channels with 15-16 bits dynamic range using IO-bit AD converters sampled every 15 ns. The function is accomplished by using a non-linear amplifier in front of the ADC to compress high amplitude signals, reversing the transformation to obtain overall linearity in a look-up table after the digitisation. The direct first-level trigger output for digitally filtered energy data is equipped with pulse recognition capability. The main data flow enters a pipeline memory from which relevant portions are extracted to second and third-level triggers via an adaptive 7-tap digital filter. The module is presently developed as 14 ASICs to be