S. Brigati

Modeling sigma-delta modulator non-idealities in SIMULINK(R)

This paper presents a complete set of SIMULINK(R) models, which allow exhaustive behavioral simulations of any sigma-delta modulator to be performed. The proposed set of models takes into account most of the sigma-delta modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier parameters (noise, finite gain, finite bandwidth, slew-rate and saturation voltages). For each model we present a description of the considered effect as well as all of the implementative details. Simulation results on a second-order switched-capacitor sigma-delta modulator demonstrate the validity of the models proposed.

A fourth-order single-bit switched-capacitor sigma-delta modulator for distributed sensor applications

In this paper we present a switched-capacitor sigma-delta modulator for high resolution applications. In particular this sigma-delta modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 /spl mu/m CMOS technology, is based on a 4th-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5 V supply and achieves a signal-to-noise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits.

A fourth-order single-bit switched-capacitor /spl Sigma/-/spl Delta/ modulator for distributed sensor applications

In this paper, we present a switched-capacitor sigma-delta (/spl Sigma/-/spl Delta/) modulator for high resolution applications. In particular, this /spl Sigma/-/spl Delta/ modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 /spl mu/m CMOS technology, is based on a fourth-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5-V supply and achieves a signal-to-noise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits.

A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

In this paper we present an integrated 155 Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip receives optical signals over a wide dynamic range (-27 dBm to 1 dBm) and temperature range (-40° C to +85° C). The chip was implemented using a sub-micron SiGe BiCMOS technology and occupies an area of 4.3 × 4.9 mm2with a power consumption of 500 mW from a supply voltage of 5 V. In the receiver analog front-end we used a low-noise wide-band transimpedance amplifier followed by a non-linear gain stage, to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts through a feedback loop the receiver threshold voltage, thus optimizing the pulse-width distortion and canceling the optical as well as the electrical offset voltages.

Modeling of fractional-N division frequency synthesizers with SIMULINK and MATLAB

Presents a set of SIMULINK models and MATLAB files, which allow exhaustive behavioral simulations of fractional-N division frequency synthesizers based on PLL. The proposed set of models takes into account most of PLLs non-idealities. For each model we present a description of the considered effect as well as all of the implementable details. Simulation results on a fractional-N division frequency synthesizer based on PLL demonstrate the validity of the models proposed.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. (Less)

An analog high-speed wide-range programmable monostable multivibrator

This paper presents a scheme for an analog monolithic monostable multivibrator suitable for use in a wide variety of applications where a need exists for pulses of a known and precise width in response to a trigger signal. The pulse can be programmed either using a reference current or an external capacitor which allow widths from 5 ns to a maximum which is limited only by capacitor values availability. The circuit was fabricated in a standard 1.2 /spl mu/m BiCMOS technology, but it is shown to be fully CMOS compatible. Measurement results indicate that very high speed is obtained at very low power dissipation and cost.

A digital front-end and readout microsystem for calorimetry at LHC

Abstract A digital solution to the front-end electronics for calorimetric detectors at future supercolliders is presented. The solution is based on high speed A D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also being considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid, is used. This solution allows a new level of integration of complex analogue and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. It also allows a high degree of programmability at both the function and the system level, and offers the possibility of customising the microsystem with detector-specific functions.

Gain enhancement technique for high-speed switched-capacitor circuits

This paper presents a novel technique for the compensation of the finite gain in active stages used in SC circuits. Simulation results are provided which show a good reduction in both module and phase errors. This technique is a good candidate to be used in high speed SC circuits where the need for a high gain-bandwidth imposes the use of low gain active stages.<<ETX>>

Digital synthesis of analog signals for audiometric applications

This paper presents a novel signal generator, based on the direct digital synthesis (DDS) technique, which fulfills the requirements of advanced audiometric systems. The described solutions face two different problems, namely the generation of a finely tunable pure sinewave and the generation of noise signals with controlled spectrum. In order to achieve tuning capabilities down to 1Hz at 20 kHz or 15 /spl mu/Hz at 100 Hz, a fractional division of a 40 MHz master clock with noise shaping of the resulting error is performed. Moreover, for noise generation a novel circuit based on pseudo-random sequences combined with analog SC filters is used.