Mahito Shinohara
Canon Inc.
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Featured researches published by Mahito Shinohara.
IEEE Transactions on Electron Devices | 1990
Nobuyoshi Tanaka; Seiji Hashimoto; Mahito Shinohara; Shigetoshi Sugawa; M. Morishita; Shigeyuki Matsumoto; Yoshio Nakamura; Tadahiro Ohmi
The BASIS (base-stored image sensor) bipolar imaging device, which consists of a bipolar phototransistor in a capacitor-loaded emitter-follower circuit, is discussed. The device is used in an imager with 310 K pixels (640 H*490 V) in a 2/3-in optical format. The imager exhibits excellent performance characteristics, such as a high aperture ratio of 60%, an image lag less than 0.1%, and good linearity with a dynamic range of 76 dB. The read out and reset operation, antiblooming capability, and total system circuit and FPN cancellation are discussed. >
international solid-state circuits conference | 2007
Hidekazu Takahashi; Tomoyuki Noda; Takashi Matsuda; Takanori Watanabe; Mahito Shinohara; Toshiaki Endo; Shunsuke Takimoto; Ryuuichi Mishima; Shigeru Nishimura; Katuhito Sakurai; Hiroshi Yuzurihara; Shunsuke Inoue
A 1/2.7 inch 1944times1092pixels CMOS image sensor with multi-gain column amplifier and double noise canceller is fabricated in a 0.18mum 1P3M CMOS process. It operates at 48MHz in a progressive scanning mode at 60fps. A 2T/pixel architecture and low optical stack with micro innerlens achieve 14.8ke<sup>-</sup>/1x-s sensitivity, 14ke<sup>-</sup> saturation, 3.7e<sup>-</sup> <sub>rms</sub> noise and 12.2e<sup>-</sup> dark current at 60degC.
international solid state circuits conference | 2007
Hidekazu Takahashi; Tomoyuki Noda; Takashi Matsuda; Takanori Watanabe; Mahito Shinohara; Toshiaki Endo; Shunsuke Takimoto; Ryuichi Mishima; Shigeru Nishimura; Katsuhito Sakurai; Hiroshi Yuzurihara; Shunsuke Inoue
A 1/2.7-in 1944 times 1484 pixel CMOS image sensor with double CDS architecture fabricated in a 0.18-mum single-poly triple-metal (1P3M) CMOS process is described. It operates at 48 MHz in a progressive scanning mode at 60 frames/s for full high-definition (HD) imaging. Two transistors/pixel architecture and low optical stack with double microlenses achieve 14.6 ke macr/1times ldr s sensitivity and 14 ke macr saturation. Double CDS architecture with a high-gain column amplifier realized a low noise floor of 3.5 e macrrms. Optimized shallow-trench isolation achieved very low dark current of 12.2 e macr/s (60degC). This image sensor also realizes low power consumption of 220 mW.
international solid-state circuits conference | 1989
Nobuyoshi Tanaka; Seiji Hashimoto; Mahito Shinohara; Shigetoshi Sugawa; M. Morishita; Shigeyuki Matsumoto; Yoshio Nakamura; T. Ohmi
A bipolar imager with an amplification function in each pixel has been developed using BiCMOS technology. The imager, which stores photocarriers in the base regions of the bipolar transistor pixels, is called the base-stored image sensor (BASIS). BASIS-type devices have been faced with three problems: (1) a reset transistor is needed in each pixel to initialize base voltage; (2) nonuniformity of offset voltage appears as fixed pattern noise; and (3) blooming is induced by intense light. Effective methods of dealing with these problems have been found. A BASIS imager with 310 k pixels in a 2/3-in optical format is described. The device specifications and characteristics of the imager are summarized.<<ETX>>
IEEE Transactions on Electron Devices | 1997
Mahito Shinohara; Shigetoshi Sugawa; Yoshio Nakamura; Tadahiro Ohmi
A new type of bipolar image detector has been developed which consists of bipolar sensor cells, bipolar frame memory cells, and signal transfer circuits. The imager with 100 H/spl times/70 V pixels was designed to detect near-infrared LED rays exactly and rapidly, and was fabricated using 2-/spl mu/m Bi-CMOS process. The device, utilizing operations specific to bipolar cells, amplifies signal charges and cancels noises to have a high signal-to-noise ratio (S/N) immune to a long time hold. It also offers several novel functions such as cancellation of external light signal, preliminary fast readout, and main readout of a selected part. Equipped with peripheral circuits, the chip is 3.66/spl times/3.7 mm in size and is very suitable for image processing use.
Archive | 1998
Mahito Shinohara; Shin Kikuchi
Archive | 1987
Hidekazu Takahashi; Mahito Shinohara
Archive | 2008
Mahito Shinohara; Shunsuke Inoue
Archive | 2003
Mahito Shinohara; Shunsuke Inoue
Archive | 2000
Seiji Hashimoto; Mahito Shinohara; Tetsunobu Kochi; Hidetoshi Hayashi