Mahroo Zandrahimi

Two effective methods to detect anomalies in embedded systems

Current-day embedded systems are very vulnerable to faults and defects. Anomaly detection is often the primary means of providing early indication of faults and defects. This paper presents two methods for detecting anomalies in embedded systems. The first method, buffer based detector, constructs a buffer consisting of events from a stream of data considered to be normal. Consequently, during test stage, if an event does not exist in the buffer, a miss will happen. An anomaly exists in test data provided that the hit rate of the buffer does not reach a predefined threshold. The second method namely probabilistic detector employs the probability of data events to evaluate the behavior of system. In order to measure the probability of events in the system, sampling of two events with distinct distance is done. Eventually, during test stage, the probability of events can be measured. An anomaly exists in test data provided that this probability does not reach a predefined threshold. A comparison between these two methods and other typical methods has been done based on detection coverage, area overhead and delay overhead. The experiments on 112 standard benchmarks show that the proposed methods can detect 100% of anomalies. Also, the area overhead of the proposed detectors grows linearly, while the area overhead of other typical detectors grows exponentially by the increase in one of the detectors parameters.

Challenges of using on-chip performance monitors for process and environmental variation compensation

Circuit monitoring techniques have been adopted widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. For cost and complexity reasons, these techniques are usually implemented by means of performance monitors allowing fast performance evaluation during production. In this paper, we demonstrate the limitations of performance monitoring methodologies in terms of accuracy and effectiveness. Silicon measurements of a nanometric FD-SOI device show that the required design margin is above 10% of the clock cycle, which leads to unacceptable waste of power.

An analysis of fault effects and propagations in ZPU: The world's smallest 32 bit CPU

This paper presents an analysis of the effects and propagations of transient faults by simulation-based fault injection into the ZPU processor. This analysis is done by injecting 5800 transient faults into the main components of ZPU processor that is described in VHDL language. The sensitivity level of various points of ZPU processor such as PC, SP, IR, Controller, and ALU against fault manifestation is considered and evaluated. The behavior of ZPU processor against injected faults is reported. Besides, it is shown that about 50.25% of faults are recovered during simulation time; 46.47% of faults are effective and the remainders 3.28% of faults are latent. Moreover, a comparison of the behavior of ZPU processor in fault injection experiments against some common microprocessors is done. The results will be used in the future research for proposing a fault-tolerant mechanism for ZPU processor.

New Switch Box Architecture for SEU Detection in SRAM-Based FPGAs

this paper proposes a method to detect Single Event Upset (SEU) faults in configuration memory of a Switch Box in SRAM-based FPGAs. A technique for mapping different patterns of a Switch Box into Boolean functions that have an interesting property, identified as self-remap, is presented, and a new architecture that exploits such property for fault detection is introduced. The architecture is validated by simulation-based fault injection tools; moreover, required area, delay and power consumption of the proposed architecture are achieved using synopsis® synthesis tool. Experimental results show that proposed architecture can detect 100% SEU faults while it imposes 150% overhead on area, 55% overhead on delay and 90% overhead on power consumption. The proposed architecture is compared with conventional fault-tolerant architectures to demonstrate its efficiency.

A Probabilistic Method to Detect Anomalies in Embedded Systems

Current-day embedded systems are very vulnerable to faults and defects. Anomaly detection is often the primary means of providing early indication of faults and defects. This paper presents a probabilistic method, which employs the probability of data events to evaluate the behavior of system. In order to measure the probability of events in the system, sampling of two events with distinct distance is done. Consequently, during test stage, the probability of events can be measured. An anomaly exists in test data provided that this probability does not reach a predefined threshold. The experiments on 112 standard benchmarks show that the proposed method can detect 100% of anomalies. Also, the area overhead of the proposed detector grows linearly, while the area overhead of other typical detectors grows exponentially by the increase in one of the detectors parameters.