Mahsa Shoaran

Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition

This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 \mbi μm CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 \mbi μW of power within an effective area of 250 \mbi μm × 250 \mbi μm per channel.

Compressive multichannel cortical signal recording

This paper presents a novel approach to acquire multichannel wireless intracranial neural data based on a compressive sensing scheme. The designed circuits are extremely compact and low-power which confirms the relevance of the proposed approach for multichannel high-density neural interfaces. The proposed compression model enables the acquisition system to record from a large number of channels by reducing the transmission power per channel. Our main contributions are the twofold. First, a CMOS compressive sensing system to realize multichannel intracranial neural recording is described. Second, we explain a joint sparse decoding algorithm to recover the multichannel neural data. The idea has been implemented at system as well as circuit levels. The simulation results reveal that the multichannel intracranial neural data can be acquired by compression ratios as high as four.

Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition

Ultra-low power circuit design techniques have enabled rapid progress in biosignal acquisition. The design of a multichannel biosignal recording system is a challenging task, considering the low amplitude of neural signals and limited power budget for an implantable system. The front-end low-noise amplifier is a critical component with respect to overall power consumption and noise of such system. In this paper, we present a new design of III-V Heterojunction TFET (HTFET)-based neural amplifier employing a telescopic operational transconductance amplifier (OTA) for multichannel neural spike recording. Exploiting the unique device characteristics of HTFETs, our simulation shows that the proposed amplifier exhibits a midband gain of 39 dB, a gain bandwidth of 12 Hz-2.1 kHz, and an input-referred noise of 6.27 μVrms, consuming 5 nW of power at a 0.5 V supply voltage. Using the proposed HTFET amplifier, a noise efficiency factor (NEF) of 0.64 is achieved, which is significantly lower than the CMOS-based theoretical limit. Design tradeoffs related to gain, power and noise requirements are investigated, based on a comprehensive electrical noise model of HTFET and compared with the baseline Si FinFET design.

A low-power area-efficient compressive sensing approach for multi-channel neural recording

High-density wireless intracranial neural recording is a promising technology enabling the autonomous diagnosis and therapy of brain diseases. Increasing the number of recording channels is accompanied by the increased amount of data resulting in an unacceptable transmission power. A comprehensive study of possible compressed sensing methods in the context of neural signals has been done, and the compression of signals originating from different channels in the spatial domain has been implemented at the system and circuit levels. Results of the simulations in a UMC 0.18μm CMOS technology and subsequent reconstructions show the possibility of compressing with ratios as high as 2.6 with a recovery SNR of at least 10dB using extremely compact and low-power circuits. The power efficiency and limited area per channel confirm the relevance of the proposed approach for multi-channel high-density neural interfaces.

Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization

The design of a high-density neural recording system targeting epilepsy monitoring is presented. Circuit challenges and techniques are discussed to optimize the amplifier topology and the included OTA. A new platform supporting active recording devices targeting wireless and high-resolution focus localization in epilepsy diagnosis is also proposed. The post-layout simulation results of an amplifier dedicated to this application are presented. The amplifier is designed in a UMC 0.18μm CMOS technology, has an NEF of 2.19 and occupies a silicon area of 0.038 mm2, while consuming 5.8 μW from a 1.8-V supply.

Structured sampling and recovery of iEEG signals

Wireless implantable devices capable of monitoring the electrical activity of the brain are becoming an important tool for understanding, and potentially treating, mental diseases such as epilepsy and depression. Compressive sensing (CS) is emerging as a promising approach to directly acquire compressed signals, allowing to reduce the power consumption associated with data transmission. To this end, we propose an efficient CS scheme which exploits the structure of the intracranial EEG signals, both in sampling and recovery. Our structure-aware approach is conceptually simple to implement in hardware and yields state-of-the-art compression rates up to 32× with high reconstruction quality, as illustrated on two human iEEG datasets.

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits. Both process variations and device mismatch have been included in this study. The performed analysis shows that while the STSCL topology is very robust against global variations mainly thanks to the adoption of an on-chip bias generator circuit, special design techniques are required to compensate for the effect of device mismatch. Proper device sizing as well as creating intentional mismatch in the biasing condition of STSCL gates are two effective approaches that have been investigated to overcome the variation related issues. Both die-to-die (D2D) and within-die (WID) variations in the delay of STSCL gates have been characterized and validated through measurements. A comprehensive analysis of timing jitter in STSCL-based ring oscillators is also presented.

Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition

Wireless implantable devices capable of monitoring the electrical activity of the brain are becoming an important tool for understanding and potentially treating mental diseases such as epilepsy and depression. While such devices exist, it is still necessary to address several challenges to make them more practical in terms of area and power dissipation. In this work, we apply Learning Based Compressive Sub-sampling (LBCS) to tackle the power and area trade-offs in neural wireless devices. To this end, we propose a low-power and area-efficient system for neural signal acquisition which yields state-of-art compression rates up to 64× with high reconstruction quality, as demonstrated on two human iEEG datasets. This new fully digital architecture handles one neural acquisition channel, with an area of 210 × 210μm in 90nm CMOS technology, and a power dissipation of only 1μW.

A Fully Integrated IC With 0.85-μW/Channel Consumption for Epileptic iEEG Detection

Feature extraction from a multichannel compressed neural signal is introduced in this brief. Compressive sensing (CS) is an efficient method for reducing the transmission data rate of sparse biological signals and lowering the power consumption of resource-constrained sensor nodes. However, recovering the original signal from compressed measurements is typically achieved by relatively complex and optimization-based algorithms, which is hardly suitable for real-time applications. The previously proposed multichannel CS scheme enables the area-efficient implementation of CS. In this brief, a low-power feature extraction method based on line length is directly applied in the compressed domain. This approach exploits the spatial sparsity of the signals recorded by adjacent electrodes of a sensor array and detects the seizure onset for every sixteen channels of the array. The proposed circuit architecture is implemented in a UMC 0.18-μm CMOS technology. Extensive performance analysis and design optimization enable a low-power and compact implementation. The proposed feature extractor reaches a perfect sensitivity of 100% for 420 h of clinical data containing 23 seizures from four patients, with an average false alarm rate of 0.34 h-1 for artifact-free channels, consuming 0.85 μW of power/channel at a compression rate of 16.

A Novel Compressive Sensing Architecture for High-Density Biological Signal Recording

The massive amount of data recorded by dense electrode arrays which are routinely connected to Nyquist-sampling signal conditioning blocks introduces new design challenges for implantable and wireless biological signal acquisition. Five different architectures of implantable multichannel neural recording systems are compared in terms of power and area constraints. Silicon results of a 16-channel spatial-domain compressive recording system implemented in a UMC 0.18 μm CMOS technology are presented. Applying intracranially recorded EEG signals, the proposed system achieves up to 16-times compression rate, consuming an extra compression power of 0.95 μW within a die area of 0.008 mm2 per channel.