Maik Stegemann
Infineon Technologies
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Publication
Featured researches published by Maik Stegemann.
Proceedings of SPIE | 2013
Marcel Heller; Dieter Kaiser; Maik Stegemann; Georg Holfeld; Nicolo Morgana; Jens Schneider; Daniel Sarlette
Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.
ieee sensors | 2014
Andre Röth; Thoralf Kautzsch; Mirko Vogt; Maik Stegemann; Heiko Fröhlich; Cornelia Breitkopf
This work presents a novel approach that utilizes amorphous hydrogenated carbon (a-C:H) layers as sacrificial structures for MEMS applications. The a-C:H layer serves as a buried sacrificial layer in the fabrication process. With the removal of the a-C:H by plasma etching processes, the movable structures are released. The fabrication of test structures is based on silicon surface micromachining technology. On those test structures, etch rates were determined for two different etch chemistries. The use of a-C:H as a sacrificial layer offers several advantages such as dry release capabilities accompanied by a high thermal and mechanical stability of the sacrificial layer and thus the possibility to integrate those layers in standard CMOS technology. Consequently, the proposed dry removal techniques prevent movable structural components from stiction problems associated with wet processing. The newly developed sacrificial layer process is suitable for a wide range of MEMS applications.
Proceedings of SPIE | 2014
Marcus Dankelmann; Markus Czekalla; Heiko Estel; Jens Hahn; Bee Kim Hong; Mario Lamm; Eric Neubert; Michael Renner; Rainer Scheibel; Maik Stegemann; Jens Schneider
The use of TiN-Hard masks for Cu metal layer patterning has become a common technique for trench first metal hard mask (TFMH) back end of line (BEOL) integration schemas. Resist rework influences the chemical and physical behavior of the TiN hard mask and therefore the final result of the dual damascene etch process in terms of critical line dimension (CD) and trench taper determining the electrical metal sheet resistance. Within this paper, the effects of three different resist rework strip procedures on subsequent TiN hard mask and dual damascene etching, using O2, H2N2 and H2O plasma processes, are compared. Furthermore, the interaction of the rework process with the CD tuning capabilities in dual damascene etch are evaluated. Summarizing the data, a stable process flow for wafers with and without resist rework is shown, eliminating litho CD rework offsets, resulting in metal trench processing with tight geometrical and electrical distributions.
Archive | 2002
Guenther Czech; Carsten Fuelber; Markus Kirchhoff; Maik Stegemann; Mirko Vogt; Stephan Wege
Archive | 2003
Maik Stegemann; Stephan Wege
Archive | 2004
Maik Stegemann; Stephan Wege
Archive | 2001
Harald Richter; Stephan Wege; Maik Stegemann
Archive | 2001
Lothar Brencher; Maik Stegemann; Uwe Rudolph
Archive | 2005
Oliver Genz; Markus Kirchhoff; Stephan Machill; Alexander Reb; Barbara Schmidt; Momtchil Stavrev; Maik Stegemann; Stephan Wege
Archive | 2000
Maik Stegemann; Uwe Rudolph; Lothar Brencher