Malgorzata Chrzanowska-Jeske

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays

This paper introduces a new design approach that combines logic and layout synthesis for Cellular-Architecture (CA) FPGAs. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly-shaped multi-level structure of (mostly) locally connected cells. This two-dimensional array of logic cells is well suited for CA-type FPGA realization. Two stages: restricted factorization and technology folding are discussed in more details. The architecture constraints and the implementation are presented for ATMEL6000 series architecture.

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints

We present a new algorithm to co-optimize test scheduling andwrapper design under power constraints for core-based SoCs(System on Chip). Core testing solutions are generated as a set ofwrapper designs, each represented by a rectangle with width equalto the test time and height equal to the number of TAM (TestAccess Mechanism) wires used. The test-scheduling problem withpower constraints is formulated as the distributed rectangle bin-packingproblem, which allows wrapper pins to be assigned to non-consecutiveSoC pins. The generalized problem for multiple-TAMsis solved by global optimization using evolutionary strategy and thesequence-pair representation. Experiments on ITCý02 benchmarksare very encouraging.

An exact algorithm to minimize mixed-radix exclusive sums of products for incompletely specified Boolean functions

An exact algorithm for the synthesis of mixed polarity exclusive sum of product (ESOP) expressions for arbitrary size incompletely specified Boolean functions is presented. For more than four input variables, this problem has not been solved yet. A decision function H is constructed for a Boolean function f that describes all possible ESOP solutions to f. The function H plays for the ESOP minimization problem a role analogous to that of the Petrick function for the minimization of the inclusive sum of product expression problem of classical logic. Each product of literals that satisfies the function H corresponds to one ESOP solution of f. The algorithms to create and solve function H are presented.<<ETX>>

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs

A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the circuit blocks) and optimizes the timing. Experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning over the classical floorplan-analyze-and-then-re-floorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12-13% smaller in area as compared to the traditional floorplanning algorithms.

Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs

We present a placement-aware 3-D floorplanning algorithm that considers 3-D-placement of logic gates inside modules for wirelength minimization. It allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. A set of vertical constraints is derived on sequence pairs of different device layers that reduces the solution space, and a fast packing algorithm with vertical constraints enables quick floorplan evaluation. Experimental results on MCNC and GSRC benchmarks show that our algorithm can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3-D floorplanning algorithms, our tool reduces the system level total wirelength by 9.8%.

Board-level multiterminal net assignment for the partial cross-bar architecture

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability

Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-based method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completely-specified Boolean functions. This is in contrast to previous incomplete circuit-based methods and complete BDD-based methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed

A regular representation for mapping to fine-grain, locally-connected FPGAs

A new data structure Pseudo-Symmetric Binary Decision Diagrams (PSBDDs) for completely specified Boolean functions has been proposed. The new diagrams are based on Ordered Binary Decision Diagrams and contact symmetric networks. The main advantages of the PSBBDs are the regular structure and predictable delay of the interconnects. These structures are especially well suited for mapping to fine-grain, locally-connected FPGAs where a very restricted routing domain limits circuit performance, for and submicron technologies.

Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts

A new kind of a decision diagrams are presented: its nodes correspond to all types of nonsingular expansions for groups of input variables, in particular pairs. The diagrams are called the Linearly Independent (LI) Decision Diagrams (LI DDs). There are 840 nonsigular expansions for a pair of variables, thus 840 different types of nodes in the tree. Therefore, the number of nodes in such (exact) diagrams is usually much smaller than the number of nodes in the well-known Kronecker diagrams (which have only single-variable Shannon, Positive Davio, and Negative Davio expansions in nodes). It is usually much smaller than 1/3 of the number of nodes in Kronecker diagrams. Similarly to Kronecker diagrams, the LI Diagrams are a starting point to a synthesis of multilevel AND/OR/EXOR circuits with regular structures. Other advantages of LI diagrams include: they generalize the well-known Pseudo-Kronecker Functional Decision Diagrams, and can be used to optimize the new type of PLAs called LI PLAs. Importantly, while the known decision diagrams used AND/EXOR or AND/OR bases, the new diagrams are AND/OR/EXOR-based. Thus, because of a larger design space, multi-level structures of higher regularity can be created with them. This paper presents both new concepts and new efficient synthesis algorithms.

Mapping of symmetric and partially-symmetric functions to the CA-type FPGAs

This paper presents a new approach to technology mapping of symmetric and partially-symmetric logic functions to Fine-Grain Cellular-Architecture FPGAs. The method is based on Ordered Binary Decision Diagrams (BDDs). Properties of symmetric functions are used to generate Reduced Ordered BDDs for symmetric and partially symmetric functions that can be easily mapped to the rectangular, locally connected arrays of CA-type FPGAs. The mapping method is presented for the existing FPGA architecture, and routing domain modification is suggested for improved mapping. Examples of FPGA layouts are given.