Alan J. Coppola

Board-level multiterminal net assignment for the partial cross-bar architecture

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

Segmented channel routability via satisfiability

Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean conditions. The routability constraint is satisfiable if and only if the net connections in the segmented channel are routable. Empirical results show that the method is time-efficient and applicable to large problem instances.

Board-level multiterminal net assignment

The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satis¿fies the equation specifies a valid routing. The approach considers all nets simultaneously and the absence of a satisfying assignment implies that the layout is unroutable. We use two of the fastest SAT solvers: Chaff and DLM to perform our experiments. Empirical re¿sults show that the method is time-efficient and applicable to large layout problem instances.

AN EXACT SOLUTION TO THE FITTING PROBLEM IN THE APPLICATION SPECIFIC STATE MACHINE DEVICE

In this paper the fitting problem for a new Application Specific State Machine Device, CY7C361, from Cypress Semiconductor is formulated and the solution is proposed. This fitting problem consists of mapping a netlist obtained from high-level synthesis into the chip’s physical resources. In general, a mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints and node multiplication (placing some nodes of the netlist graph in more than one node of the physical graph). Such formulation is quite general for a class of Complex Programmable Logic Device (CPLD) fitting problems, and has not been found in the literature. We implemented an exact, constraint-based, tree searching algorithm with several kinds of backtracking.

An exact algorithm for the technology fitting problem in the application specific state machine device

The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Semiconductor is formulated, and a solution is proposed. This fitting problem consists of mapping the netlist obtained from high-level synthesis into the chips physical resources. In general, the mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints. The formulation is quite general for a class of electronically programmable logic device (EPLD) fitting problems. An exact, constraint-based, tree searching algorithm with several kinds of backtracking was implemented.<<ETX>>

On segmented channel routability

We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field programmable gate arrays (FPGAs). Our approach transforms the routing task into a single large Boolean equation such that any assignment of input variables that satisfies the equation specifies a valid routing. It considers all nets simultaneously and the absence of a satisfying assignment implies that the channel is unroutable. Empirical results show that the method is time-efficient and applicable to large problem instances.