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Featured researches published by Mamoru Kurata.


IEEE Transactions on Electron Devices | 1989

Self-consistent particle simulation for (AlGa)As/GaAs HBTs with improved base-collector structures

Riichi Katoh; Mamoru Kurata; Jiro Yoshida

A one-dimensional self-consistent particle simulator was developed for (AlGa)As/GaAs heterojunction bipolar transistors (HBTs) to investigate how far the device performance can be improved by positively utilizing non-equilibrium electron transport phenomena under a heavily doped base condition. Computation was thus carried out for HBTs with various categories of base and collector structures. The electron transport mechanisms are discussed in detail according to the results in conjunction with the reduction in base-to-collector transit time.


IEEE Transactions on Electron Devices | 1984

Modeling and characterization for high-speed GaAlAs-GaAs n-p-n heterojunction bipolar transistors

Mamoru Kurata; J. Yoshida

A numerical one-dimensional model is employed to predict dc and switching characteristics for n-p-n type GaAlAs-GaAs transistors, including heteroemitter-homocollector and heteroemitter-heterocollector junction structure, where four kinds of doping profiles are considered. Also, Si and GaAs homojunction transistors are referred to for comparison. Switching performance is discussed for a single unit case, with and without a base resistance, and for a DCTL-type two-stage inverter case, including the delay time dependence on fanout.


Solid-state Electronics | 1976

One-dimensional calculation of thyristor forward voltages and holding currents

Mamoru Kurata

Abstract One-dimensional numerical analysis of complete semiconductor device equations is applied to the p-n-p-n four layer structure with an arbitrary impurity doping profile and arbitrary carrier lifetimes, to calculate the thyristor DC forward voltages and the holding current. In the beginning, a numerical method of the current-control type is presented, with discussion about the convergence of the iterative process involved. Then a set of standard numerical values is given to the parameters to describe the impurity doping condition. Computation results are demonstrated for a variety of carrier lifetimes and current densities. Endeavor will be made to understand basic device physics through the computed carrier densities, electric fields, potentials and currents. The computation results also include the static current vs voltage characteristics, which are immediately concerned with the actual design and fabrication of thyristors. Specifically for the design of high speed thyristors, a preferable condition is provided by keeping lifetimes in the shorter base to a high value and those in the longer base to a low value.


IEEE Transactions on Electron Devices | 1981

2500-V 600-a gate turn-off thyristor (GTO)

Makoto Azuma; Mamoru Kurata; Katsuhiko Takigami

GTO self-turn-off capability provides an advantage over an ordinary thyistor, because of forced commutation circuit removal upon inverter and chopper application, thus substantially reducing equipment size, weight, and mechanical noise. A series of high-power GTOs has been developed, with the present 2500-V-600-A unit as its peak. The most essential design problem for this unit is to establish a principle for increasing maximum gate turn-off current (IATO), while keeping overall thyristor characteristics in reasonable balance. High IATOwas attained by decreasing p-base sheet resistance, as well as decreasing n-emitter finger width. Excellent thyristor characteristics were obtained by adopting a low acceptor concentration near the cathode-gate junction. From a device process point of view, introducing a phosphorus redeposition annealing increased carrier lifetime in the p base to a sufficiently high level. This process contributed most strikingly to improving the off-state voltage.


international electron devices meeting | 1985

Experimental and numerical study of non-latch-up bipolar-mode MOSFET characteristics

Akio Nakagawa; Yoshihiro Yamaguchi; Kiminori Watanabe; Hiromichi Ohashi; Mamoru Kurata

Bipolar-Mode MOSFET characteristics were experimentally and numerically analyzed. It was found that parasitic pnp transistor common base current gain of greater than 0.27 is necessary to realize low forward voltage drop, because carrier distributions are different from those for diodes. It was also found that three decay phases can be distinguished in the turn-off current waveform. A critical current-voltage border beyond which avalanche injection occurs was obtained from the model analysis. Safe operating areas for Non-Latchup Bipolar-Mode MOSFETs are also presented. Current concentration hardly occurs in Bipolar-Mode MOSFETs if avalanche injection is avoided.


power electronics specialists conference | 1974

A new cad-model of a gate turn-off thyristor

Mamoru Kurata

A new CAD-model of a GTO-thyristor has been developed, including non-linear junction recovery, lateral currents through the conductivity-modulated base layers and external circuit conditions. Computed results give a real time transient response of charges, currents and voltages. A comparison will be made between theoretical and experimental results of a test sample. Agreement is shown to be satisfactory for a quantitative estimation of the actual device characteristics. Further, turn-off time variation due to device parameter fluctuations will be predicted for wide p-base samples.


IEEE Transactions on Electron Devices | 1989

Self-consistent particle simulation for (AlGa)As/GaAs HBTs under high bias conditions

Riichi Katoh; Mamoru Kurata

Nonequilibrium electron transport phenomena in the emitter and collector regions under high bias conditions were investigated for standard N-p-n (AlGa)As/GaAs heterojunction bipolar transistors (HBTs) by utilizing a previously developed one-dimensional self-consistent particle simulator. A dramatic increase in the cutoff frequency was observed for a lightly doped collector HBT as the current density increased over 10/sup 5/ A/cm/sup 2/, where the collector transit time was reduced due to the extension of the velocity overshoot region in the collector corresponding to the decrease in electric field near onset of the Kirk effect. A saturation tendency was seen in the collector current versus base-to-emitter bias voltage (V/sub BE/) characteristic for high V/sub BE/, where V/sub BE/ exceeded the base-to-emitter built-in voltage of the conduction band. Simulations indicate that this feature is caused by electron velocity saturation in the neutral n-type (AlGa)As emitter region. >


IEEE Transactions on Electron Devices | 1972

Design considerations of step recovery diodes with the aid of numerical large-signal analysis

Mamoru Kurata

Switching behavior of the step recovery diode (SRD) is studied through exact large-signal analysis. Two numerical methods are presented. One is suitable for steady-state and slow-transient calculations, while the other is based on a principle given by Scharfetter and Gummel, being appropriate for fast-transient calculation. Criteria for each method are described in terms of space and time intervals. A variety of doping profiles is generated by seven parameters, to determine the influence of each parameter on switching response. The normally defined transition time for current falloff from 90 to 10 percent consists of a physical transition phase and the phase of the CR time constant, which is defined as the product of junction capacitance and series resistance. The former is minimized by a narrow region of light doping, or by an abrupt profile, whereas the latter is minimized by a wide region of light doping, thus making a compromise necessary. Under the assumption of improved device fabrication technology, operation with low external impedance will allow total transition time to decrease to about one-half or one-third of todays standard sample. As was pointed out by Moll et al., a small amount of series inductance is desirable for fast transition.


IEEE Transactions on Electron Devices | 1990

A model-based comparison of AlInAs/GaInAs and InP/GaInAs HBT's: a Monte Carlo study

Riichi Katoh; Mamoru Kurata

The high-speed performances of AlInAs/GaInAs and InP/GaInAs heterojunction bipolar transistors (HBTs) are investigated using a one-dimensional self-consistent particle simulator. Optimum alloy compositions for a graded-gap base structure are obtained for both transistors through the tradeoff between the emitter-charging time and base transit time. The saturation velocity in the GaInAs n-type collector is found to be smaller than that in InP, which has been attributed to the diffusion of a large number of hot back-scattered Gamma -valley electrons in the GaInAs collector. The difference in the collector transit time in p-type collectors is trivial, since the maximum electron velocity was restricted to below 1.2*10/sup 8/ cm/s due to a strong nonparabolicity effect. The cutoff frequency for the former and the latter are estimated to be 2 and 1.5 times higher, respectively, than for AlGaAs/GaAs HBTs. These results are attributed to a larger bandgap difference between the emitter and base, to yield a high base built-in field, rather than a larger Gamma -L band separation energy in the collector to enhance the velocity overshoot effect. >


Solid-state Electronics | 1974

A computer study of power-limiter diode behavior

Mamoru Kurata

Abstract High frequency, large-signal behavior of a PIN -diode is studied on the basis of an exact numerical analysis of the one-dimensional device equations, including avalanche multiplication phenomena. Numerical methods are briefly described and discussion is made about their proper usage for obtaining correct solutions. A series of computation results will be presented about a shunt-diode limiter of an X-band frequency range. Diode voltage- and current waveforms will be observed at various input-power levels, along with the underlying internal carrier dynamics. Endeavor is made to figure out mechanisms which are responsible for the power-limiting character of the diode. The numerical simulation is shown to provide, even with a simple circuit configuration, an identity to the experimental results of semi-quantitative order, verifying its utility as an aid for device design and fabrication.

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Hiromichi Ohashi

National Institute of Advanced Industrial Science and Technology

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