Kiminori Watanabe

Ultra-low on-resistance LDMOS implementation in 0.13µm CD and BiCD process technologies for analog power IC's

Toshibas 5th generation BiCD/CD-0.13 is a new process platform for analog power applications based on 0.13µm CMOS technology. The process platform has six varieties of rated voltage, 5V, 6V, 18V, 25V, 40V, and 60V. 5 to 18V CD-0.13 process use P-type silicon substrate. 25 to 60V BiCD-0.13 process use N-Epi wafer with N+/P+ buried layer on P type silicon substrate. Each LDMOS recode ultra-low on-resistance compared with that of previous papers, and we will realize the highest performance analog power ICs using this technology.

1800V bipolar-mode MOSFETs: A first application of silicon wafer direct bonding (SDB) technique to a power device

1800v and 1700v non-latch-up Bipolar-Mode MOSFETs have been developed, based on Silicon Wafer Direct Bonding (SDB) technique: a new substrate wafer fabrication process superior to conventional epitaxy. The SDB technique easily realizes an optimum N buffer structure as well as a high resistivity N-layer. Self-aligned deep P+diffusions, densified hole bypasses and an amorphous silicon resistive field plate have been implemented. 0.45µsec fall-time and more than 100A maximum current capability have been successfully realized.

Experimental and numerical study of non-latch-up bipolar-mode MOSFET characteristics

Bipolar-Mode MOSFET characteristics were experimentally and numerically analyzed. It was found that parasitic pnp transistor common base current gain of greater than 0.27 is necessary to realize low forward voltage drop, because carrier distributions are different from those for diodes. It was also found that three decay phases can be distinguished in the turn-off current waveform. A critical current-voltage border beyond which avalanche injection occurs was obtained from the model analysis. Safe operating areas for Non-Latchup Bipolar-Mode MOSFETs are also presented. Current concentration hardly occurs in Bipolar-Mode MOSFETs if avalanche injection is avoided.

Cost-effective air-gap interconnects by all-in-one post-removing process

Low process cost air-gap structure for multilevel interconnect system is proposed by all-in-one post-removing process. Problems regarding the air-gap process were studied and solutions for moisture uptake and for metal wiring oxidation were developed. The proposed air-gap process is compatible with the conventional BEOL process. Furthermore, this process can build the air-gap structure with least additional process steps, and it tolerates misalignment.

500V three phase inverter ICs based on a new dielectric isolation technique

500V three-phase inve r t e r ICs for DC brushless motor dr ives has been developed, for t h e first t i m e , using a new d ie l ec t r i c isolat ion method based on s i l icon w a f e r direct-bonding(D1SDB). The new D I method has an advantage t h a t it is completely compatible with conventional junction i so l a t ion and Resurf principle. been developed without using c a r r i e r lifetime con t ro l process. Thus, t h e developed I C s can be fabricated using only conventional LSI processes. operate at 16kHz PWM frequency, and realize compact low noise DC brushless motors when ins t a l l ed inside t h e motor. function is also proposed. 600V high speed lateral IGBTs has The developed 500V i nve r t e r I C s A new shor t c i r cu i t protect ion

Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond

In order to realize highly reliable low-k/Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65 nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replaced by the hybrid-DD structure with PAr/SiOC stack films. It shows high extendibility to the next generation using newly developed technologies, such as eBeam cure and damage restoration techniques.

Two types of 500 V double gate lateral N-ch bipolar-mode MOSFETs in dielectrically isolated p/sup -/ and n/sup -/ silicon islands

Two types of 500-V double-gate lateral N-ch bipolar-mode MOSFET (metal-oxide-semiconductor field effect transistor), fabricated on dielectrically isolated p/sup -/ and n/sup -/ silicon islands, were compared. It was found that electrical characteristics for devices on p/sup -/ silicon islands are superior to those of counterpart devices on n/sup -/ silicon islands. It was also shown that double gate operation improves the device tradeoff relation, realizing 200-ns fall time and 0.075- Omega cm/sup 2/ on-resistance-area product. The devices were passivated by SIPOS resistive field plates, which allow series connection by metal interconnection layers without breakdown voltage reduction.<<ETX>>

0.6 /spl mu/m BiCMOS based 15 and 25 V LDMOS for analog applications

In the present paper, we report the development of complementally 25 V LDMOS, 15 V n-ch LDMOS, 18 V npn/pnp and 5 V CMOS. The developed LDMOS achieved high on-state breakdown voltages for the gate voltage of 5.0 V. The on-resistance values of the developed 15 V and 25 V n-ch LDMOS achieves 22.7 and 27.5 mn mm/sup 2/, respectively. The characteristics of bipolar transistors and CMOS are also sufficiently good.

Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond

Silicide-cap for Cu interconnects is promising for enhancing electromigration (EM) performance for 32 nm-node and beyond. But the trade-off properties of silicide-cap between line resistance and EM lifetime remain to be resolved. Increasing of line resistance is caused by Si diffusion in Cu line. So, we focused on Ti barrier metal (BM), which diffuses in Cu line, and applied it in combination with silicide-cap, in order to keep Si stable at the surface of Cu line. As a result, we achieved EM median time-to-failure (MTF) 100 times longer than that of the sample w/o silicide-cap and Ta-BM while line resistance is kept lower. Activation energy (Ea of EM of 1.45 eV is achieved.

High voltage, new driver IC technique based on silicon wafer direct-bonding (SDB)

Two fundamental techniques are presented for high-voltage driver ICs: dielectric isolation based on silicon wafer direct-bonding (DISDB) and a high-voltage junction termination technique (SIPOS resistive field plate). The SIPOS plate shields the external electric field influence on breakdown voltage. DISDB integrates low-voltage logic and high-voltage (500 V) devices and has three structural variations corresponding to different application fields.<<ETX>>