Manabu Kusumoto

Coupling Analysis of PCB-Chassis Systems with Signal Lines and Via Structures using SPICE

This paper describes the SPICE modeling of printed circuit boards (PCBs) with signal lines and via structures electrically connected to a metal chassis. First, a PCB model is proposed considering the coupling between signal lines and the power bus due to via structures. Next, the model is expanded to include the chassis and grounding posts. The calculated results using SPICE are shown to be consistent with experimental data. Furthermore, positioning of the grounding posts near the edges of the PCB is shown experimentally and numerically to reduce radiated emissions.

Investigation of electromagnetic noise coupling that affects packet error rates in wireless-LAN mounted printed circuit boards

This paper shows experimental results of packet error rates (PERs) in wireless-LAN mounted printed circuit boards and gives a discussion on a channel of electromagnetic noise coupling that affects the PER. We utilize the amplitude probability distribution (APD), a statistical and quantitative method for noise evaluation, to investigate the noise coupling channel. Evaluation results indicate that the noise transmitting space and coupling to an antenna cause an increase of the PER.

Power integrity estimation by use of LSI power-pin model applying chip-package-board co-design

This paper describes a fast board-power-voltage fluctuation analysis system to realize the chip-package-board co-design. As high-speed signal processing of semiconductor chips and high-density packaging technologies are progressed, circuit margins are reduced and the packaging design becomes difficult more and more. These difficulties often bring re-designs of board and package layouts. To reduce the time loss by the rework and increase design efficiency, short turn-around-time estimation techniques for analyzing the electrical performance integrating chip-package-board characteristics have been required. This system contributes to the increase of design efficiency in the early product development stage followed by reducing the time loss due to the rework in the development process.

Fast power integrity estimation method by use of LSI power-pin model

Fast power integrity analysis system to realize the chip-package-board co-design is described. As high-speed signal processing of semiconductor chips and high-density packaging technologies are progressed, circuit margins are reduced and the packaging design becomes difficult more and more. These difficulties often bring re-designs of board and package layouts. Short turn-around-time estimation techniques for analyzing the electrical performance integrating chip-package-board characteristics have been required for reducing the time loss by the rework and increase design efficiency,. This system contributes to the increase of design efficiency in the early product development stage followed by reducing the time loss due to the rework in the development process.