Hiroshi Wabuka

A multilayer board-type magnetic field probe with high spatial resolution and RF current estimation method for ICs

The authors describe how NEC and NEC Glass Components Co. Ltd. developed a magnetic field probe with high spatial resolution enabling the measurement of magnetic fields near IC packages and dense-printed circuit boards (PCBs) so that RF currents can be estimated. The design of the magnetic field probe is based on a multilayer board, and achieves spatial resolutions at least 1.8 times those of previous probes, as well as a reduction by up to 30% in the external dimensions of the detection unit (loop area is 0.2 x 8.4 mm). They also developed a test-board design and a magnetic-field measuring method over a printed wiring pattern (microstrip line) which can be applied to LSI testers.

FDTD/spl I.bar/SPICE analysis of EMI and SSO of LSI ICs using a full chip macro model

A method of macro modeling the power and ground circuits of an LSI IC taking into account internal gates has been proposed. Major contributors to simultaneous switching output noise (SSO) and electromagnetic interference (EMI) are the power and ground currents of clock circuits in internal gates which are modeled using simple flip-flop circuits by summing their gate widths and interconnection capacitances. Using such a macro model, methods for reducing SSO and EMI for such LSI chips are analyzed by FDTD/spl I.bar/SPICE. It is shown that the major contributor to SSO and EMI is not I/O circuitry but internal gates. The most effective way to reduce such noise is to implement large decoupling capacitors into a chip.

SPICE simulation of power supply current from LSI on PCB with a behavioral model

This paper proposes a new behavioral model of an LSI to simulate current in the power supply line of a PCB. The models impedance changes with time, thus ensuring simulation accuracy. The new model makes it possible to easily simulate the current in a PCB power supply line. Good agreement is obtained between simulated values and measured in experiments.

Realizing the V80 and its system support functions

An overview is given of the architecture of an overall design considerations for the 11-unit, 32-b V80 microprocessor, which includes two 1-kB cache memories and a branch prediction mechanism that is a new feature for microprocessors. The V80s pipeline processing and system support functions for multiprocessor and high-reliability systems are discussed. Using V80 support functions, multiprocessor and high-reliability systems were realized without any performance drop. Cache memories and a branch prediction mechanism were used to improve pipeline processing. Various hardware facilities replaced the usual microprogram to ensure high performance.<<ETX>>

LSI immunity test method by direct GND pin injection

This paper proposed a method to test the immunity of LSIs where RF noise is injected into the GND pin of an LSI. We concluded that the GND pin injection test we propose is more suitable for evaluating actual LSI immunity against RF noise than the VDD pin injection test based on conventional Direct RF Power Injection (DPI).

Power integrity estimation by use of LSI power-pin model applying chip-package-board co-design

This paper describes a fast board-power-voltage fluctuation analysis system to realize the chip-package-board co-design. As high-speed signal processing of semiconductor chips and high-density packaging technologies are progressed, circuit margins are reduced and the packaging design becomes difficult more and more. These difficulties often bring re-designs of board and package layouts. To reduce the time loss by the rework and increase design efficiency, short turn-around-time estimation techniques for analyzing the electrical performance integrating chip-package-board characteristics have been required. This system contributes to the increase of design efficiency in the early product development stage followed by reducing the time loss due to the rework in the development process.

Chip complexity requires signal and power integrity

With an increase in operating frequency and the complexity of system on a chip (SOC), it becomes important to consider the noise generated along the signal and power/ground interconnections that leads to malfunction. We have developed a new simulation method for the full chip-level signal and power-integrity analysis. The CAD layout data is converted into SPICE transmission line models considering silicon substrate effects. To remove the limitation of size and complexity of layout data in the real LSI chips, a sectioning method using MOR with super linear solver has been introduced. The proposed method can also be extended to the computation of current/voltage distributions leading to EMI analysis