Mani Soma

Analog and mixed-signal benchmark circuits-first release

The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductors 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

Extraction of peak-to-peak and RMS sinusoidal jitter using an analytic signal method

This paper proposes a new method based on analytic signal theory for extracting both instantaneous and RMS sinusoidal jitter from PLL output signals. The method relies on the extension of a real signal into an analytic signal by utilizing the Hilbert transform. Both the theoretical basis and fundamental concepts of the proposed method are explained. A review of conventional testing methods is also presented. Results of Matlab simulations validate the performance of the proposed method for measuring random jitter. The method is further validated by comparing experimental sinusoidal jitter results with those measured with a time interval analyzer.

Automatic analog test signal generation using multifrequency analysis

A new multifrequency test generation technique for detecting catastrophic and parametric failures in this class of circuits is presented. Testability transfer factors for circuit elements are introduced and we use them to construct an efficient dynamic test set. Fault detectability and fault coverage are also defined. We also describe the signature analysis methodology used to evaluate the generated test set. Circuits from the suite of analog and mixed-signal benchmark circuits are used to validate our approach. The approach presented may be used to construct input signals for the selection of an external stimulus applied through an arbitrary waveform generator.

Dynamic testing of ADCs using wavelet transforms

This paper introduces a new method for evaluating non-idealities in ADCs using wavelet transforms. Compared with conventional testing methods, this method can shorten the test time and improve test quality during production testing of ADCs.

An effective defect-oriented BIST architecture for high-speed phase-locked loops

We propose a new method of defect-oriented testing of PLL using charge-based frequency measurement BIST (CF-BIST) technique. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST for a PLL is possible. Fault simulations using the 900 MHz PLL from National Semiconductor Corp. show higher fault coverage than previous test methods.

Dynamic life-estimation of CMOS ICs in real operating environment: precise electrical method and MLE

The functionality of an IC in field use can be maintained by replacing an IC shortly before its anticipated failure. An accurate estimation of circuit lifetime is important in selecting a replacement time to: (1) avoid unanticipated circuit failure by replacing them as early as possible; and (2) use the IC fully by replacing them as late as possible. Since the problem is different from lifetime estimation with accelerated test results, this approach continually measures circuit performance and then analyzes the measurements statistically. The whole estimation process is covered from selection of circuit parameters for performance measurement to development of an aging model for the statistical analysis. The circuit-delay change due to hot-carrier effects is selected to quantify the performance degradation; an aging model, founded on the hot-carrier induced failure mechanism, is developed. Maximum likelihood estimation (MLE) is used for the statistical characteristics of future aging, where the severity of the operating environment is assumed to be a stationary random process. The MLE are used to choose an efficient time for IC replacement. The practical use of the suggested method in IC maintenance is demonstrated with statistically simulated data.

Experimental results for current-based analog scan

This paper presents the design of current-mode circuits for analog scan, which include the highly accurate current-mirror scan latches and the analog shift registers. Experimental data from a test chip fabricated in Orbit 2-micron CMOS Foresight process illustrates that the accuracy of the circuits is sufficient for use in analog on-chip scan-based testing. The interface between analog scan and the P1149.4 test bus is discussed to show system-level applications of this technique.