Manish Goel

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Forward error correction decoding for WiMAX and 3GPP LTE modems

In this paper, we review the requirements for forward error correction (FEC) decoding for next generation wireless modems-mobile Worldwide Interoperability for Microwave Access (WiMAX) and third generation partnership project long term evolution (3GPP LTE). FEC decoder consists of mainly three components: control channel decoder, data channel decoder, and hybrid automatic repeat query (HARQ) combining. Control channel decoder is constrained by latency budget which impacts buffering as well as power management of modem signal processing chains. For WiMAX, both Viterbi and Turbo decoders are required to receive control channel while for LTE, only Viterbi decoder is required. For data-channel, a high-throughput Turbo decoder is required to support high data rate. HARQ combining is mainly dominated by memory size and bandwidth requirements given the maximum data rate, maximum number of HARQ processes and re-transmission formats. We analyze the requirements and discuss possible candidate architectures for three components.

Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes

Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decoding features such as end-state forcing and best-state trace back is presented. Second, simple predecoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0:9V TI 45-nm CMOS process at 100MHz for Long Term Evolution (LTE) [1] as application. More than 90% power saving is achieved with predecoding at a throughput of 120 Mbps and 0:2 dB SNR loss for 10−5 frame error rate.

A high performance split-radix FFT with constant geometry architecture

High performance hardware FFTs have numerous applications in instrumentation and communication systems. This paper describes a new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm is known to have lower multiplicative complexity than both radix-2 and radix-4 algorithms. However, it conventionally involves an “L-shaped” butterfly datapath whose irregular shape has uneven latencies and makes scheduling difficult. This work proposes a split-radix datapath that avoids the L-shape. With this, the split-radix algorithm can be mapped onto a constant geometry interconnect structure in which the wiring in each FFT stage is identical, resulting in low multiplexing overhead. Further, we exploit the lower arithmetic complexity of split-radix to lower dynamic power, by gating the multipliers during trivial multiplications. The proposed FFT achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.

Coding for jointly optimizing energy and peak current in deep sub-micron VLSI interconnects

In deep sub-micron processes, on-chip interconnect is becoming the delay bottleneck and predominant source of power consumption. Simultaneous switching of large buses pose a great challenge on peak current as well. In this paper, we present a novel bus coding technique, based on transition pattern codes (TPC), to perform joint optimization. A TPC scheme has been constructed employing a joint cost function on energy and peak current. The encoder and decoder of the code has been synthesized using a commercial 28nm process and the power, delay and area overhead has been evaluated. HSPICE simulations in 28nm show up to 70% reduction in peak current and 15% reduction in energy consumption compared to an uncoded bus.