Seok-jun Lee

Microwatt embedded processor platform for medical system-on-chip applications

A medical system-on-chip (SoC) that integrates an ARM Cortex-M3 processor is presented. Ultra-low power operation is achieved via 0.5–1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Forward error correction decoding for WiMAX and 3GPP LTE modems

In this paper, we review the requirements for forward error correction (FEC) decoding for next generation wireless modems-mobile Worldwide Interoperability for Microwave Access (WiMAX) and third generation partnership project long term evolution (3GPP LTE). FEC decoder consists of mainly three components: control channel decoder, data channel decoder, and hybrid automatic repeat query (HARQ) combining. Control channel decoder is constrained by latency budget which impacts buffering as well as power management of modem signal processing chains. For WiMAX, both Viterbi and Turbo decoders are required to receive control channel while for LTE, only Viterbi decoder is required. For data-channel, a high-throughput Turbo decoder is required to support high data rate. HARQ combining is mainly dominated by memory size and bandwidth requirements given the maximum data rate, maximum number of HARQ processes and re-transmission formats. We analyze the requirements and discuss possible candidate architectures for three components.