Manoj Franklin

High-bandwidth data memory systems for superscalar processors

This paper considers the design of a data memory hierarchy, with a level 1 (L1) data cache at the top, to support the data bandwidth demands of a future-generation superscalar processor capable of issuing about ten instructions per clock cycle. It introduces the notion of cache bandwidfh — the bandwidth with which a cache can accept requests from the processor — and shows how the bandwidth of a standard, blocking cache, can degrade greatly because of its inability to overlap the service of misses. Non-blocking or lockup-free caches are discussed as a way of reducing the bandwidth degradation due to misses. To improve the data bandwidth to greater than 1 request per cycle, multi-port, interleaved caches are introduced. Simulation results from a cycle-by-cycle simulator, using the MIPS R2000 instruction set, suggest that memory hierarchies with blocking L 1 caches will be unable to support the bandwidth demands of futuregeneration superscalar processors. Multi-port, nonblocking (MPNB) L1 caches introduced in this paper for the top of the data memory hierarchy appear to be capable of supporting such data bandwidth demands.

The Expandable Split Window Paradigm for Exploiting Fine-grain Parallelism

We propose a new processing paradigm, called the Expandable Split Window (ESW) paradigm, for exploiting fine-grain parallelism. This paradigm considers a window of instructions (possibly having dependencies) as a single unit, and exploits fine-grain parallelism by overlapping the execution of multiple windows. The basic idea is to connect multiple sequential processors, in a decoupled and decentralized manner, to achieve overall multiple issue. This processing paradigm shares a number of properties of the restricted dataflow machines, but was derived from the sequential von Neumann architecture. We also present an implementation of the Expandable Split Window execution model, and preliminary performance results.

Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors

Traditionally, register files have been the primary agent for inter-operation communication in load/store architectures. As processors start issuing multiple instructions per cycle, a centralized register file can easily become a bottleneck. This paper analyzes the register filetrafficin a load/store architecture with a view to motivate the development of alternate inter-operation communication mechanisms that reduce the bandwidth demanded of a centralized register file. We firstprovide metrics to characterize the register traffic. These metrics deal with the degree and locality of use of the register instances created. We then present the results of a simulation study that uses the MIPS R2000 architecture and the SPEC benchmark programs. We have two major results. First, a large number of the register instances are used only once, and the average degree of use of register instances is about 2. Second, most of the register instances are used up soon after they are created (within about 30-40 instructions). This suggests that alternate inter-operation communication mechanisms that exploit the temporal locality of use of register instances are likely to be effective in reducing the traffic burden on the centralized register file. The second result was pivotal in the design of the distributed register filefor the multiscalar processing paradigm.

A study of time-redundant fault tolerance techniques for high-performance pipelined computers

A class of fault-tolerance techniques using time redundancy can be a viable alternative for high-performance pipelined processors. Time-redundant fault-tolerance techniques, such as recomputing with shifted operands (RESO), have not been very popular, partly because of the perceived time overhead of such techniques. While the per-instruction time overhead can be quite high, especially if the degree of pipelining is low, the overhead can be very small (and possibly negligible) when the execution of an entire program is considered and the degree of pipelining is high. Simulation studies were carried out on the Cray-1 scalar unit using the well-known Livermore loops as benchmarks to determine the performance loss due to time-redundant fault-tolerance techniques. The results show that the overhead for such techniques is less than 10% in almost all cases and is negligibly small in most cases. This suggests that time-redundant techniques can be useful for fault tolerance in high-performance scalar processors with multiple pipelined functional units.<<ETX>>

The expandable split window paradigm for exploiting fine-grain parallelsim

We propose a new processing paradigm, called the Expandable Split Window (ESW) paradigm, for exploiting fine-grain parallelism. This paradigm considers a window of instructions (possibly having dependencies) as a single unit, and exploits fine-grain parallelism by overlapping the execution of multiple windows. The basic idea is to connect multiple sequential processors, in a decoupled and decentralized manner, to achieve overall multiple issue. This processing paradigm shares a number of properties of the restricted dataflow machines, but was derived from the sequential von Neumann architecture. We also present an implementation of the Expandable Split Window execution model, and preliminary performance results.

Built-in self-testing of random-access memories

Built-in self-test (BIST) methods are examined, including the fault models and the test algorithms on which the BIST implementations are based. The notion of generic test architectures suitable for implementing a wide variety of test algorithms is introduced. A taxonomy for test architectures is provided and used to categorize BIST implementations, and important implementations are surveyed. It is demonstrated that BIST is a viable solution to the problem of testing large memories and that approaches based on test architectures rather than on test algorithms are more versatile and will likely predominate in the future.<<ETX>>

Design of a BIST RAM with row/column pattern sensitive fault detection capability

A novel fault model is developed for random-access memories for a class of pattern-sensitive faults called row/column weight-sensitive faults. A test procedure is developed to detect faults from the defined fault model. This test sequence also tests the memory array for the 5-cell-neighborhood static pattern-sensitive faults and other faults, such as stuck-at-faults and coupling faults. A built-in self-test (BIST) version of the algorithm has been implemented by completing the logic design and layout in 2- mu m CMOS technology. The silicon area overhead for a 4M RAM is as little as 0.8%. The number of extra pins can be as low as one if clock is available on-chip. The number of extra pins can be as low as one if clock is available on-chip. The delay introduced to the normal paths, as estimated by simulation tools, is small and can be reduced even further.<<ETX>>

Row/column pattern sensitive fault detection in RAMs via built-in self-test

Row-pattern-sensitive and column-pattern-sensitive faults in random-access memories (RAMs) are the class of faults in which the contents of a cell are assumed to be sensitive to the contents of the row and column containing the cell. Although the existence of such faults has been argued in the literature, tests to detect such faults have been proposed. The authors formally define a fault model based on the row and column pattern sensitivity. They establish a lower bound on the length of a test sequence required to detect such faults and propose algorithms that generate test sequences of the required length. Although the length of the test sequence is O(N/sup 3/2/), where N is the number of bits in the RAM, the authors believe that the algorithm can be used to test RAMs in built-in self-test environments.<<ETX>>

Parallel computation of LFSR signatures

Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost a factor of n, where n is the number of processors used. This parallel algorithm is designed by dividing that total number of time-frames to be simulated into partitions, and assigning each partition to a processor. Each processor determines the contribution of its partition to the final signature, and the contributions of different processors are merged, with very little effort, to obtain a single signature. The speedup given by our parallel algorithm is over and above any speedups provided by other sequential speedup techniques such as the use of lookup tables. We also present the results of a simulation study showing the speedup achieved by the parallel algorithm on a Sequent multiprocessor system.<<ETX>>

Pattern sensitive fault testing of RAMs with built-in ECC

The problem of testing RAMs with different built-in error-correction-coding (ECC) capabilities is formulated. The basics of ECC in RAMs are reviewed, and some of the implementation aspects are described. It is shown that if memories using separable linear codes satisfy certain conditions, it is always possible to apply arbitrary patterns to all check bits. An upper bound on the number of writes required to apply the required patterns to a neighborhood is established. An efficient algorithm for testing the information bits and check bits of an N-bit memory array for 5 cell neighborhood pattern sensitive faults in O(N) reads and writes is provided. The use of the method is demonstrated by a case study.<<ETX>>