Kozo Kinoshita

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M<N test vectors, without loss of fault coverage. During test generation, we also find a lower bound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.

On low-capture-power test generation for scan testing

Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0s and 1s to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.

Low-capture-power test generation for scan-based at-speed testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0s and 1s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss

Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large lower bounds on the minimum test set size. Experimental results of test generation demonstrate the effectiveness of the heuristics.

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them. >

A new ATPG method for efficient capture power reduction during scan testing

High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness

CIRCUIT DESIGN FOR BUILT-IN CURRENT TESTING

In current testing, the number of test vectors is usually A testing circuit for built-in current testing is proposed and a test generation method using the testing circuit is described. The function of the testing circuit is to measure the integral of the current including the dynamic current during a certain time interval and to judge whether the Cuir is fault-free or not by the measured value. The function01 speed of the testing circuit is rapid because this measuring method is not influenced by any dy,rlamic current. We also describe the test generation method briefly. The test sequences cause almost equal dymmic current between every two test vectors. The number of test vectors in each test sequence is less than that of the traditional testing for stuck-at faults.

A method for identifying robust dependent and functionally unsensitizable paths

It has been shown previously that a logic circuit often contains a large number of logical paths that need not be tested to verify the timing behavior of the circuit, if the other paths are robustly tested. These paths are called robust dependent. A subset of the robust dependent paths are the functionally unsensitizable paths. This paper proposes a method for efficiently identifying both types of paths. The proposed procedure uses local circuit analysis to keep the run time relatively low, and relatively independent of the number of paths in the circuit. The method may not identify all the paths that are robust dependent or functionally unsensitizable, however, experimental results show that the numbers it finds are comparable, and sometimes even higher than those found by other methods. The procedure can be applied to circuits that cannot be handled by other methods.

Built-In Self-Testing RAM: A Practical Alternative

The article investigates the design of a built-in self-testing RAM as an economical way, in terms of silicon area overhead, to test memories¿more economical than the use of external testers. The design of a BIST static RAM is given, along with design decisions, retrospectives on how design could have used the area even more efficiently, and results of implementation. The extra silicon area used by the BIST hardware for 64K static memories is only five percent; for larger memories, it is less. BIST RAM, then, is a practical alternative, especially since testing can be done even during burn-in without the aid of an expensive external tester.

Easily Testable Sequential Machines with Extra Inputs

In this paper, an easily testable machine is defined as one which possesses: 1) a distinguishing sequence of length [log2 n] which forces the machine into a specific state S1, and 2) transfer sequences of length at most [1og2 n] to carry the machine from state S1 to state Si for all i. A design procedure is presented in which an arbitrary machine is augmented to an easily testable machine by adding two special input symbols to the original machine. An efficient procedure is also described for designing checking experiments for the easily testable machines. For an n-state, m-input symbol machine, this procedure gives a bound on the length of the checking experiment that is approximately mn[log2,n]. Furthermore, the total checking experiments are preset.