Manoranjan Pradhan

High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics

This article presents the design of a new high-speed multiplier architecture using Nikhilam Sutra of Vedic mathematics. The proposed multiplier architecture finds out the compliment of the large operand from its nearest base to perform the multiplication. The multiplication of two large operands is reduced to the multiplication of their compliments and addition. It is more efficient when the magnitudes of both operands are more than half of their maximum values. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The multiplier circuit is synthesised and simulated using Xilinx ISE 10.1 software and implemented on Spartan 2 FPGA device XC2S30-5pq208. The output parameters such as propagation delay and device utilisation are calculated from synthesis results. The performance evaluation results in terms of speed and device utilisation are compared with earlier multiplier architecture. The proposed design has speed improvements compared to multiplier architecture presented in the literature.

Novel binary divider architecture for high speed VLSI applications

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel Binary divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary recursion through Vedic division methodology. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx ISE using 9Onm CMOS technology. The propagation delay of the resulting 8-bit binary dividend by an 4-bit divisor circuitry was only ~19.9ns and consumed ~34mW power for a LUT Utilization of 23/1536. By combining Boolean logic with ancient Vedic mathematics, substantial amount of iteration were eliminated that resulted in ~46% reduction in delay and ~27% reduction in power compared with the mostly used (Repetitive subtraction method) architecture.

Implementation of Modular Multiplication for RSA Algorithm

This paper presents the architecture and modeling of modular multiplication for RSA public key algorithm. It supports multiple lengths like 128 bits, 256 bits, 512 bits of data. In this paper simple shift and add algorithm is used to implement the modular multiplication. It makes the processing time faster and used comparatively smaller amount of space in the FPGA due to its reusability. Each block is coded with Very High Speed Integrated Circuit Hardware Description Language. The VHDL code is synthesized and simulated using Xilinx-ISE 10.1.

MAC Implementation using Vedic Multiplication Algorithm

The paper presents the implementation of MAC (multiplieraccumulator) unit using Vedic multiplier. The speed of MAC depends on the speed of the multiplier. The Vedic multiplier uses “Urdhva Tiryagbhyam” algorithm. The proposed MAC unit is coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. The MAC is implemented on a FPGA device XC2S200-6PQ208 using Xilinx ISE10.1 tool. The proposed design shows improvement of speed over the design presented in [1]. General Terms Algorithms.

Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier

In this paper, the authors have compared the efficiency of the Karatsuba multiplier using polynomial multiplication with the multiplier implementing Vedic mathematics formulae (sutras), specifically the Nikhilam sutra. The multipliers have been implemented using Spartan 2 xc2s200 pq208 FPGA device having speed grade of -6. The proposed Karatsuba multiplier has been found to have better efficiency than the multipliers involving Vedic mathematics formulae. General Terms Karatsuba algorithm, Vedic multiplier, classical multiplication.

Simulation and Verification of Self Test 16-Bit Processor

paper presents the design and verification of 16 bit processor. The Booth multiplier and restoring division are integrated in to the ALU of the proposed processor. The processor is described in structural level to verify the general understanding of the system. The processor has 16-bit instruction based on three different format R-format, I-format and J-format. The control unit generates all the control signals needed to control the coordination among the entire component of the processor. All the modules in the design are coded in VHDL (very high speed integrated circuit hardware description language) to ease the description, verification, simulation and hardware implementation. The design entry, synthesis, and simulation of processor are done by using Xilinx ISE 10.1 software and implemented on XC2S200-6pq208 Spartan-II FPGA device.

Efficient ASIC and FPGA implementation of cube architecture

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix-2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field-programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high-speed application in microprocessor environment.

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

Efficient hardware realization of signed arithmetic operation using IEN

For implementation of a fast arithmetic algorithm and efficient hardware realization, signed digit representation is crucial. Redundant binary (RB) and 2s complement number representation is the most widely used technique for representation signed digit number. The drawbacks of RB technique include multi valued logic as well as need of unconventional hardware blocks. Though 2s complement notation is efficient and commonly applicable, it needs further optimization in terms of delay and area. In this paper we proposed binary arithmetic operation using inverted encoding of negabits (IEN), where arithmetic value -1 (0) is represented for 0 (1). The proposed IEN adder is simulated using ISim simulator and synthesized using xc4vlx15-12sf363 FPGA device. The proposed work is verified in terms of utilizing the same hardware blocks as that of conventional signed digit representations. The use of IEN representation advances the signed value in comparison with 2s complement number representation.

Synthesis Methods of Baugh-Wooley Multiplier and Non-restoring Divider to Enhance Primitive’s Results of QCA Circuits

As a semiconductor industry continues growing toward miniaturization and high speed, it is challenged by the rising uncertainties in the scaling for further devices shrink in the nanometer scale. Scaling leads to quantum effect at the nanoscale. Quantum dot cellular automata (QCA) is the alternative approach to synthesize the digital logic circuits with high density and high computation speed. In this paper, an accurate approach to synthesize and optimize the Baugh-Wooley multiplier and non-restoring divider in the presence of QCA technology has been proposed. The proposed designs are robust and utilize a wire-crossing type of single layer, with minimal clock phasing. The synthesis approach and optimization are perfectly scalable across layout construction of designs and can find better primitive’s results of QCA circuit performance.