Bandan Kumar Bhoi

Novel binary divider architecture for high speed VLSI applications

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel Binary divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary recursion through Vedic division methodology. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx ISE using 9Onm CMOS technology. The propagation delay of the resulting 8-bit binary dividend by an 4-bit divisor circuitry was only ~19.9ns and consumed ~34mW power for a LUT Utilization of 23/1536. By combining Boolean logic with ancient Vedic mathematics, substantial amount of iteration were eliminated that resulted in ~46% reduction in delay and ~27% reduction in power compared with the mostly used (Repetitive subtraction method) architecture.

Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the n-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground ...

Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellular Automata

The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this way, the state-of-the-art technology such as QCA was forced toward high-speed computing with negligible energy dissipation in the physical foreground. This work targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates and QCA implementation. This divider circuit inherits many benefits such as fewer garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.

Synthesis Methods of Baugh-Wooley Multiplier and Non-restoring Divider to Enhance Primitive’s Results of QCA Circuits

As a semiconductor industry continues growing toward miniaturization and high speed, it is challenged by the rising uncertainties in the scaling for further devices shrink in the nanometer scale. Scaling leads to quantum effect at the nanoscale. Quantum dot cellular automata (QCA) is the alternative approach to synthesize the digital logic circuits with high density and high computation speed. In this paper, an accurate approach to synthesize and optimize the Baugh-Wooley multiplier and non-restoring divider in the presence of QCA technology has been proposed. The proposed designs are robust and utilize a wire-crossing type of single layer, with minimal clock phasing. The synthesis approach and optimization are perfectly scalable across layout construction of designs and can find better primitive’s results of QCA circuit performance.

Novel Robust Design for Reversible Code Converters and Binary Incrementer with Quantum-Dot Cellular Automata

This work, we employ computing around quantum-dot automata to construct the architecture of the reversible code converters and binary incrementer. The code converter and binary incrementer are made up of Feynman gate and Peres gate, respectively. We have presented the robust design of Ex-OR in QCA, which is used for the construction of code converters and binary incrementer. The layouts of proposed circuits were made using the primary elements such as majority gate, inverter, and binary wire. A novel binary-to-gray converter design offers 59% cell count reduction and 36% area reduction in primitives improvement from the benchmark designs. Being pipeline of PG gate to construct the 1-bit, 2-bit, and 3-bit binary incrementer, we can use this robust layout in the QCA implementation of binary incrementer. By the comparative result, it is visualized that the binary incrementer such as 1-bit, 2-bit, and 3-bit achieved 60.82, 60.72, and 64.79% improvement regarding cell count from the counterpart.

A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testability of Building Blocks in Quantum Circuit

The reversible logic circuit is popular due to its quantum gates involved where quantum gates are reversible and noted down feature of no information loss. In this paper, parity preserving reversible binary-to-BCD code converter is designed, and effect of reversible metrics is analyzed such as gate count, ancilla input, garbage output, and quantum cost. This design can build blocks of basic existing parity preserving reversible gates. The building blocks of the code converter reversible circuit constructed on Toffoli gate based as well as elemental gate based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.

Design of Conservative Gate and their Novel Application in Median Filtering in Emerging QCA Nanocircuit

In this era of emerging technology, fault-tolerant logic is applied for circuit design. As the deep submicron and scaling, a number of pitfalls are the faces of the CMOS technology. So a lot of constraints related to CMOS have shorted with the quantum-dot cellular automata (QCA) technology. In this work, a new parity conservative gate referred as parity-QCA (P-QCA) is proposed. The gate is simulated with QCADesigner and compared with existing parity preserving logic gates. By the comparative outcomes, it is found that the proposed design achieved higher efficiency as compared to the counterparts. We achieved 100% stuck-at fault coverage.

An efficient redundant binary adder with revised computational rules

Abstract Redundant binary representation (RBR) offers a carry-free addition of two redundant binary (RB) numbers. The computational rules of the conventional RB adder (CRBA) generate intermediate sum and carry vectors in RBR, leads to area overhead and pre-hardware elements for reverse conversion (RC). We have considered that the intermixing of inverted encoding of negabits (IEN) representation and conventional binary bits or posibits can be realized using standard hardware blocks. This paper provides a new computational rule for RB adder generating the intermediate sum and intermediate carry in posibit and IEN representations replacing the redundant digits. Thus, the proposed RB adder provides a single stage RB adder omitting the requirement of intermediate RB digits. For circuit synthesis of the proposed designs, we have considered Encounter® RTL Compiler and Xilinx Synthesis Technology in ASIC and FPGA platforms respectively. The comparative study of proposed NRBA offers improved design parameters as compared to CRBA.

Design and evaluation of an efficient parity-preserving reversible QCA gate with online testability

Abstract The current monolithic integrated circuits revolution has been growing over past few decades, but the VLSI industry faces problems in the domain of short channel effect, device density, and scaling along with power consumption. Hence research is a need to investigate alternative nanoelectronics technology such as Quantum-dot cellular automata (QCA). This paper presents a novel reversible gate with a parity-preserving property realized using QCA technology. Results demonstrate that the proposed gate is more efficient compared to the existing parity-preserving reversible gate designs regarding the area, delay, and power consumption. To facilitate online fault detection of the proposed gate, two new reversible parity generator and parity checker circuits are proposed. The proposed even parity generator succeeded in achieving 62.5% cell count, and 23.07% area from prior works. These two circuits are designed using a new ultra-efficient exclusive-OR (XOR) gate, designed with only 11 cells with an area of 0.02 μm2. We also present an efficient fault-tolerant reversible D-latch using the proposed gate. The QCADesigner and HDLQ tools are used for designing the QCA layouts and for the functional verification of the proposed circuits, respectively. Energy dissipation analysis of the proposed gate is performed using the QCAPro simulation tool.

An improved FPGA based model for automatic traffic sign detection

This paper describes a vital algorithm designed on a single integrated circuit chip. Using this chip, the traffic signals are monitored automatically depending on the mass of vehicles crossing a particular lane. It not only saves valuable time but also reduces the human which is highly required in this busy world. The other vital function of the chip is that it serves as an automatic traffic sign detector. The images of the traffic signs are processed by the chip to categorize the signs under a known category. This involves the use of image processing techniques. This function of the chip reduces human error related issues by alerting the vehicles driver to react on time thus reducing the potential traffic accidents The chip is so designed that when compared to all its previous counterparts it takes very little amount of time. Thus the chip serves the purpose of automatic traffic sign detector, when embedded in a vehicle. This results in area and cost reduction in designing the chip which is always looked for by any designer.