Manpreet S. Khaira

Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking

This paper presents the formal verification of all sub-circuits in a floating-point arithmetic unit (FPU) from an Intel microprocessor using a word-level model checker. This work represents the first large-scale application of word-level model checking techniques. The FPU can perform addition, subtraction, multiplication, square root, division, remainder, and rounding operations; verifying such a broad range of functionality required coupling the model checker with a number of other techniques, such as property decomposition, property-specific model extraction, and latch removal. We will illustrate our verification techniques using the Weitek WTL3170/3171 Sparc floating point coprocessor as an example. The principal contribution of this paper is a practical verification methodology explaining what techniques to apply (and where to apply them) when verifying floating-point arithmetic circuits. We have applied our methods to the floating-point unit of a state-of-the-art Intel microprocessor, which is capable of extended precision (64-bit mantissa) computation. The success of this effort demonstrates that word-level model checking, with the help of other verification techniques, can verify arithmetic circuits of the size and complexity found in industry.

Word level model checking—avoiding the Pentium FDIV error

The highly-publicized division error in the Pentium has emphasized the importance of formal verification of arithmetic circuits. Symbolic model checking techniques based on binary decision diagrams (BDDs) have been successful in verifying control logic. However, lack of proper representation for functions that map boolean vectors into the integers has prevented this technique from being used for verifying arithmetic operations. We have developed a new technique for verifying arithmetic circuits. The new technique, called word level model checking, has been used successfully to verify circuits for division and square root computation that are based on the SRT algorithm used by the Pentium. The technique makes it possible to handle both the control logic and the data paths in the circuit. The total number of state variables exceeds 600 (which is much larger than any circuit previously handled by other symbolic model checkers).

Logic verification of very large circuits using Shark

In this paper, we will present Shark, a software based logic verification technology that allows high-performance switch-level simulation of multi-million transistor circuits on general-purpose workstations. Shark achieves high-performance simulations on very large circuits through three key technologies: 1) a circuit partitioner based on latch boundary components, design hierarchy driven clustering, and latch/activity load balancing, 2) a high-performance switch-level simulator capable of simulating very large models and run word-parallel simulations, and 3) a simulation backplane that can connect any number of simulators to form a distributed/parallel simulation environment. Shark has been tested on circuits of up to 15 M transistors. On an Intel circuit with about 5 M transistors, Shark achieved a simulation throughput of 19 Hz.

Micro-2010: lead performance microprocessor of the year 2010-myth or reality?

Can you imagine working on a PC powered by a processor with 100 BIPS (Billion Instructions Per Sec) of performance? Is a processor with 1 Billion transistors a reality? This talk describes what the Micro-2010 will be like and identifies the challenges involved in its design. We expect all aspects of life to be impacted by Micro-2010. Applications like tele-presence, augmented reality, and reality animation indicate that such microprocessor performance will be a critical enabling technology. This talk makes an attempt to describe the characteristic features of the microprocessors of 2010, and identifies the challenges involved in their design and test. Micro-2010 will run at a frequency in excess of 4 gigaHertz. Getting to that level of performance while meeting the power budget (<100 Watts) and area budget (<

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500 cost) will require breakthroughs in circuit design methodologies, CAD tools and technologies, and process technology. If current design methodology trends continue, designing Micro-2010 will require every single VLSI design engineer graduating after 2005 to be hired into the team designing it! This implies that major breakthroughs in design methodology, enabled by a new generation of CAD tools, is essential for these designs to become a reality. The semiconductor process in 2010 will have a minimum feature size less than 0.1 micron and the transistors a gate oxide of the thickness of less than the height of 10 layers of silicon dioxide molecules. These dimensions are smaller than the wavelength of visible light and will require major breakthroughs in process technology. Given the expected volume of shipment of Micro-2010, an errata like the FDIV cannot be tolerated without severe financial ramifications. Avoiding errata in a 1 Billion Transistor design is practically impossible. The talk will identify specific research directions in the areas of design and CAD tools to meet the challenges of design of the Micro-2010 and propose potential solutions.