Mansour H. Assaf

Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits. This paper reports new space compression techniques which facilitate designing such circuits using compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The compaction techniques utilize the concepts of Hamming distance, sequence weights, and derived sequences in conjunction with the probabilities of error occurrence in the selection of specific gates for merger of a pair of output bit streams from the CUT. The outputs of the space compactor may eventually be fed into a time compactor (viz. syndrome counter) to derive the CUT signatures. The proposed techniques guarantee simple design with a very high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with numerous examples. Specifically, extensive simulation runs on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST programs confirm the usefulness of the suggested approaches.

Testing Analog and Mixed-Signal Circuits with Built-In Hardware - A New Approach

This paper aims to develop an approach to test analog and mixed-signal embedded-core-based system-on-chips (SOCs) with built-in hardware. In particular, oscillation-based built-in self-test (OBIST) methodology for testing analog components in mixed-signal circuits is implemented in this paper. The proposed OBIST structure is utilized for on-chip generation of oscillatory responses corresponding to the analog-circuit components. A major advantage of the OBIST method is that it does not require stimulus generators or complex response analyzers, which makes it suitable for testing analog circuits in mixed-signal SOC environments. Extensive simulation results on sample analog and mixed-signal benchmark circuits and other circuits described by netlist in HSPICE format are provided to demonstrate the feasibility, usefulness, and relevance of the proposed implementations

A novel approach to designing aliasing-free space compactors based on switching theory formulation

This paper suggests a novel approach to designing zero-aliasing space compactors utilizing switching theory concepts of Hamming distance, sequence weights, cover table and frequency ordering, together with concept of Nth order missed error probability estimates under stochastic dependence of line errors for detectable single stuck line faults of the CUT. The advantages of aliasing-free space compaction over earlier techniques are evidently clear-zero-aliasing is achieved without any modifications of the CUT, the area overhead and signal propagation delay are relatively less compared to conventional parity tree linear compactors, and the approach used works equally well with both deterministic and pseudorandom test sets.

Space compression revisited

This paper discusses new space compression techniques for built-in self-testing (BIST) of VLSI circuits based on the use of compact test sets to minimize the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The techniques utilize the concepts of Hamming distance and sequence weights along with failure probabilities of errors in the selection of specific gates for merger of pairs of output streams from the CUT. The outputs coming out of the space compressor may eventually be fed into a time compressor to derive the signature for the circuit. The concept is extended to establish generalized mergeability criteria for merging an arbitrary number of output bit streams under conditions of both stochastic independence and dependence of line errors. The proposed techniques guarantee rather simple design with high fault coverage for single stuck-line faults, with low CPU simulation time and acceptable area overhead. Design algorithms are also proposed, and the simplicity and ease of implementation are demonstrated with examples, primarily through extensive simulation runs on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST. The paper also provides performance comparisons of the designed space compressors with the conventional linear parity tree space compressor.

Sensor based home automation and security system

The conventional design of home security systems typically monitors only the property and lacks physical control aspects of the house itself. Also, the term security is not well defined because there is a time delay between the alarm system going on and actual arrival of the security personnel. This paper discusses the development of a home security and monitoring system that works where the traditional security systems that are mainly concerned about curbing burglary and gathering evidence against trespassing fail. The paper presents the design and implementation details of this new home control and security system based on field programmable gate array (FPGA) The user here can interact directly with the system through a web-based interface over the Internet, while home appliances like air conditioners, lights, door locks and gates are remotely controlled through a user-friendly web page. An additional feature that enhances the security aspect of the system is its capability of monitoring entry points such as doors and windows so that in the event any breach, an alerting email message is sent to the home owner instantly.

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets

The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context. This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible.

Fault simulation and response compaction in full scan circuits using HOPE

This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of design space-efficient support hardware for built-in self-testing of VLSI circuits. The techniques utilized in the paper take advantage of sequence characterization developed previously by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors, and then apply these concepts to the case of full scan sequential benchmark circuits using the fault simulator HOPE.

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

The synthesis of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits, and a number of efficient algorithms have been proposed. The paper reports new techniques that facilitate designing such space-efficient BIST support circuits using knowledge of compact test sets, with the target objective of minimizing the storage requirements for the circuit under test (CUT), while retaining the fault coverage information. The suggested techniques take advantage of some well-known concepts of conventional switching theory, particularly those of cover table and frequency ordering, as commonly utilized in the minimization of switching functions, in conjunction with a new measure of failure probability in case of stochastic dependence of line errors, besides knowledge of Hamming distance, sequence weights, and derived sequences as previously used by the authors in sequence characterization, in the selection of specific logic gates for merger of an arbitrary number of output bit streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compactor to derive the CUT signatures. The techniques give good design with high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are provided, and the simplicity and ease of their implementations are demonstrated. In particular, the paper gives results on extensive simulation runs on the ISCAS 85 combinational benchmark circuits with ATALANTA, FSIM, and COMPACTEST programs.

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the synthesis of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). An approach to designing zeroaliasing space compaction hardware in relation to embedded cores-based SOC is proposed in this paper for single stuck-line faults, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) using new graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits, with programs ATALANTA and FSIM.

Space compaction under generalized mergeability

Generalized mergeability criteria for merging an arbitrary number of output sequences have been established under conditions of stochastic dependence and independence of line errors. In this paper, the authors report experimental results on ISCAS 85 benchmark circuits which were targeted for space compaction using these generalized mergeability criteria.