Satyendra N. Biswas

An adaptive compressed MPEG-2 video watermarking scheme

Digital watermarking is becoming more and more important for protecting the authenticity of multimedia objects as they become easier to copy, exchange, and modify. Several watermarking schemes have been proposed in recent years, but most of them deal with still images, only some being extended over to the temporal domain for video watermarking. But again most of those approaches are applied to uncompressed video processing domain. In the subject paper, a new compressed video watermarking procedure is proposed. The developed method embeds several binary images, decomposed from a single watermark image, into different scenes of a video sequence. The spatial spread spectrum watermark is embedded directly into the compressed bit streams by modifying discrete cosine transform (DCT) coefficients. In order to embed the watermark with minimum loss in image fidelity, a visual mask based on local image characteristics is incorporated. Extensive experimental simulations demonstrate that the proposed watermarking scheme is substantially more effective and robust against spatial attacks such as scaling, rotation, frame averaging, and filtering, besides temporal attacks like frame dropping and temporal shifting.

Testing Analog and Mixed-Signal Circuits with Built-In Hardware - A New Approach

This paper aims to develop an approach to test analog and mixed-signal embedded-core-based system-on-chips (SOCs) with built-in hardware. In particular, oscillation-based built-in self-test (OBIST) methodology for testing analog components in mixed-signal circuits is implemented in this paper. The proposed OBIST structure is utilized for on-chip generation of oscillatory responses corresponding to the analog-circuit components. A major advantage of the OBIST method is that it does not require stimulus generators or complex response analyzers, which makes it suitable for testing analog circuits in mixed-signal SOC environments. Extensive simulation results on sample analog and mixed-signal benchmark circuits and other circuits described by netlist in HSPICE format are provided to demonstrate the feasibility, usefulness, and relevance of the proposed implementations

Space Compactor Design in VLSI Circuits Based on Graph Theoretic Concepts

The realization of space-efficient support hardware for built-in self-testing (BIST) is of great significance in VLSI circuits design. New approaches to designing aliasing-free space compaction hardware are proposed in the subject paper for testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory, viz. those of cover table, frequency ordering commonly utilized in the simplification of switching functions, and of incompatibility relation to generate maximal compatibility classes using graph theoretic concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper provides briefly the mathematical basis of selection criteria for merger of an optimal number of outputs of the circuit under test (CUT) to achieve maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits with programs ATALANTA and FSIM. The advantages of the suggested approaches are evident in achieving zero aliasing without any CUT modifications, while keeping the area overhead and signal propagation delay relatively low, besides their applicability with both deterministic compacted and pseudorandom test patterns

Sensor based home automation and security system

The conventional design of home security systems typically monitors only the property and lacks physical control aspects of the house itself. Also, the term security is not well defined because there is a time delay between the alarm system going on and actual arrival of the security personnel. This paper discusses the development of a home security and monitoring system that works where the traditional security systems that are mainly concerned about curbing burglary and gathering evidence against trespassing fail. The paper presents the design and implementation details of this new home control and security system based on field programmable gate array (FPGA) The user here can interact directly with the system through a web-based interface over the Internet, while home appliances like air conditioners, lights, door locks and gates are remotely controlled through a user-friendly web page. An additional feature that enhances the security aspect of the system is its capability of monitoring entry points such as doors and windows so that in the event any breach, an alerting email message is sent to the home owner instantly.

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the synthesis of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). An approach to designing zeroaliasing space compaction hardware in relation to embedded cores-based SOC is proposed in this paper for single stuck-line faults, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) using new graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits, with programs ATALANTA and FSIM.

MPEG-2 digital video watermarking technique

For protecting the authenticity of multimedia objects, watermarking plays a vital role, since, they are much easier to get copied, exchanged and modified these days. Conventional watermarking techniques as available are not always competent enough to protect the authenticity of multimedia objects as they are usually applied in the uncompressed domain. To address this deficiency, the subject paper presents a new compressed domain video watermarking scheme. The method proposed herein embeds several binary images decomposed from a single watermarked image into different scenes in a video sequence. The spatial spread spectrum watermark is embedded directly into the compressed bit streams by modifying the discrete cosine transform coefficients. In order to embed the watermark with minimum loss in image fidelity, a visual mask based on local image characteristics is incorporated. Simulation experiments demonstrate that the developed technique yields effective and robust protection against conventional spatial strikes, viz. scaling and frame averaging besides temporal attacks.

Further Studies on Zero-Aliasing Space Compression Based on Graph Theory

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the realization of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-onboard to system-on-chip (SOC). This paper revisits the problem of designing zero-aliasing space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing new graph theory concepts, based on optimal generalized sequence mergeability as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximal compaction ratio in the design, along with some experimental results on ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA and FSIM.

System-on-chips Design Using ISCAS Benchmark Circuits - An Approach to Fault Injection and Simulation Based on Verilog HDL

Abstract The evolution of the embedded cores-based design paradigm in recent times has created numerous challenging problems for the test design community. To develop suitable test environment and appropriate test methodologies for digital cores-based system-on-chip (SOC) is a fascinating area of research today. This paper attempts to develop viable solution option to these problems based on cores constructed from the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be Institute of Electrical and Electronics Engineers P1500-compliant. The cores and test access mechanism (TAM) are described in the paper using Verilog hardware description language, while TAM is implemented as a plain signal transport medium, being shared by all the cores in the SOC. The fault injection is done by a simulator that also generates the tests for the core. The fault simulation process is carried out after successful compilation of the cores, the individual core selection being done by the program running in the background.AbstractUsage of Automatic Speech Recognition (ASR) systems is increasing day-by-day for voice centric applications in mobile handheld and Voice over Internet Protocol (VoIP) devices. The necessity is also increasing to find out the ASR performance under different network impediments. Among them, speech and audio coding standards is the one, which affects the ASR performance greatly, when, using them with different sampling and bit rates in the practical systems. Another common impediment which influences the ASR accuracy is the bit errors in the wireless networks and packet drop conditions in the VoIP networks. ASR performance with some of the speech coding standards under noise conditions for the wireless networks is reported in the literature. However, each study is reporting the ASR performance for few narrowband codecs with different speech databases and different ASR toolkits like RAPHEL, HTK, SPHINX, etc. In this paper, the analysis on ASR performance while using both narrowband and wideband speech...

A Software-Based Method for Test Vector Compression in Testing System-on-a-Chip

A new software-based hybrid test vector compression method for testing system-on-a-chip (SOC) using an embedded processor is presented in this paper. In the proposed approach, a software program is first loaded into the on-chip processor memory core together with the compressed test data set. In order to reduce on-chip storage as well as testing time, the large volume of test data input is compressed in a hybrid fashion before being downloaded into the processor. The method combines a set of adaptive coding techniques for the required test data compression. The compression program, however, need not be loaded into the embedded processor, since only the decompression of test data is necessary for application by the automatic test equipment (ATE). Most importantly, this software-based hybrid scheme requires minimal hardware overhead, while the on-chip embedded processor core can be reused for normal operation after the testing is completed. In the paper, only the compression part of the technique is presented, and the efficiency of the suggested hybrid approach is demonstrated through simulation experiments on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits

Designing home security and monitoring system based on field programmable gate array

ABSTRACT In the conventional design of home security systems, only the property is typically monitored, without taking into consideration the physical control aspects of the house itself. Besides, the term security is not strictly well defined in view of the fact that there is usually a time delay between the alarm system going on and actual arrival of the security personnel. This paper presents the development of a home security and monitoring system that is suitable where the traditional security systems that are mostly concerned about curbing burglary, gathering evidence against trespassing and so on fail. The design and implementation details of this new home control and security system which is based on field programmable gate array has been discussed in the subject paper. The user here can interact directly with the system through a web-based interface over the Internet, while home appliances like air conditioners, lights, door locks, and gates are controlled remotely through a user-friendly web page. An additional feature that enhances the security aspect of the system is its capability to monitor entry points such as doors and windows so that in the event of any breach, an alerting email message could be sent to the home owner instantly.