Manuel Cabanas-Holmen

Heavy Ion, High-Energy, and Low-Energy Proton SEE Sensitivity of 90-nm RHBD SRAMs

We measure the sensitivity of different 90-nm SRAM cells to single-event upsets (SEUs) caused by heavy ions, high energy protons, and low energy protons. We discuss radiation hardened by design techniques that impact SEU sensitivity.

Heavy Ion and High Energy Proton-Induced Single Event Transients in 90 nm Inverter, NAND and NOR Gates

We measure heavy ion and proton-induced SETs in inverters, and NAND and NOR gates from a 90 nm RHBD library. NAND and NOR gates have higher SET cross section and generate wider pulses than inverters.

Clock and Reset Transients in a 90 nm RHBD Single-Core Tilera Processor

A complex processor was synthesized using an RHBD cell library and fabricated in a commercial 90 nm CMOS technology. Single Event Effects testing revealed transients on the clock and global reset signals. These critical circuits will receive additional hardening in the next prototype design.

Predicting the Single-Event Error Rate of a Radiation Hardened by Design Microprocessor

We describe the approach used to calculate and verify on-orbit upset rates of radiation hardened microprocessors. System designers use these error rates to choose between microprocessors and add appropriate system-level recovery and redundancy.

Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing

We introduce the 32 nm SOI Boeing Interleaved Flip-Flop, which is based on the DICE topology with additional RHBD layout enhancements. Sensitive node pairs were separated by interleaving elements of the flip-flop cell, to attain the required SEU performance while minimizing the area, speed and power impact. The Boeing Interleaved Flip-Flop takes advantage of the reduced charge sharing inherent to an SOI technology to maintain a two order of magnitude SEU improvement relative to the unhardened flip-flop, which corresponds to more than an order of magnitude SEU rate reduction compared to our 90 nm DICE.

At-Speed SEE Testing of RHBD Embedded SRAMs

We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell Upsets (MCU), Multiple Bit Upsets (MBU), persistent errors and transient errors. Error Detection and Correction (EDAC) can reduce the residual error rate due to SEU by multiple orders of magnitude. Consequently, careful testing of the at-speed test structure is essential to detect and quantify the risk of rare, uncorrectable MBU.

A method for efficient Radiation Hardening of multicore processors

This paper describes a method for developing Radiation Hardened by Design (RHBD) multicore processor Integrated Circuits (ICs) that meet specific single-event error rate targets in space environments with minimal impacts on power, area, and speed.

Total Ionizing Dose Characterization of an 8-bit 200-MSps Switched-Capacitor Pipeline A-to-D Converter in 32nm SOI CMOS

A Radiation-Hardened By Design 8-bit 32nm SOI CMOS pipeline ADC shows no AC performance nor non-linearity worsening vs. TID when operated at 200MSps sampling rate, -1dBFS sinewave input amplitude. The circuit shows no visible performance variation during irradiation, and maintains >42dBFS SNR, >61dBc SFDR up to 1Mrad(Si) after LMS (Least Mean Square) gain and offset calibration techniques are applied.

Single-event effects characterization of a 12-bit 200MSps A-to-D converter in 32nm SOI CMOS with MilliBeam™ and broad-beam heavy-ions

A 12-bit 32nm SOI CMOS pipeline ADC clocked at 200 MSps was tested at LBNL with the MilliBeam™ technique and showed no upsets with LET up to 30.9 MeV·cm²/mg (Kr), while 1-sample SETs up to 600 LSB in amplitude were observed with broad-beam exposure at TAMU with 0°, 60° incidence angles (Xe and Au), and LET up to 170 MeVcm²/mg.

Estimating SEE Error Rates for Complex SoCs With ASERT

This paper describes the ASIC Single Event Effects (SEE) Error Rate Tool (ASERT) methodology to estimate the error rates of complex System-on-Chip (SoC) devices. ASERT consists of a top-down analysis to divide the SoC into sensitive cell groups. The SEE error rate is estimated with a bottom-up calculation summing the contribution of all sensitive cell groups, including derating and utilization factors to account for the probability that a cell-level error has a SoC-level impact. The sensitive cell SEE rates are evaluated using test data from specially designed test structures. Standard rate estimation tools are augmented with novel rate estimation approaches for direct proton upsets and for spatial redundancy.