Manuel Jaramillo

Combined pattern collapse and LWR control at the 70 nm node through application of novel surface conditioner solutions

As pattern collapse and line width roughness (LWR) become critical lithography challenges, there is growing interest in applying surface conditioner solutions during the post-develop process to address BOTH these issues. In this paper, we patterned 90nm 1:1.2 lines/spaces (L/S) on 200mm wafers and 70nm dense lines on 300mm wafers to evaluate the combined performance of pattern collapse and LWR using newly formulated surface conditioners. The performance of each conditioner was compared to the standard formulation, which is capable of significant pattern collapse reduction, but affords no LWR improvement. These newly improved formulations enabled a ~20% LWR reduction for 90nm features and a ~10% LWR reduction for 70nm dense lines. In addition, the new formulations significantly enlarged the LWR and CD process windows for 70nm dense lines, as demonstrated by a 50% increase of maximum depth of focus (DOF) over the standard formulation.

Surface conditioning solutions to reduce resist line roughness

In this study, surface conditioning solutions were used during post-develop process to enhance the 193 nm lithography performance. These solutions were applied to the wafer surface in a surface treatment step between the DI water rinse and drying steps. Compared to the standard develop process, the formulated surface conditioning solution enabled a 24% reduction in line width roughness, particularly in the high frequency roughness components. The solution also improved the pattern collapse performance by enlarging the non-collapse window and extending the minimum CD feature size by 10 nm. Additional benefits provided by the formulated surface conditioner solution were minimal changes to CD and resist profile.

Formulated surface conditioners to enhance the non-collapse window and maintain defect control : A bi-functional approach for sub-100-nm lithography

One key challenge in sub-100 nm lithography is line pattern collapse. Pattern collapse has become an obstacle in device manufacturing processes requiring dense-high aspect ratio resist lines. In addition to pattern collapse, defect control continues to be a factor in IC manufacturing. In this study, the impact of a formulated surface conditioner, OptiPatten® Clear, with bifunctional capabilities: improved non-collapse window and defect control, was tested using a 193 nm lithographic process. To determine pattern collapse performance, 100 nm dense lines/space (L/S) and 100 nm 1:0.9 L/S were patterned into 240 nm of resist on 200 mm wafers. The wafers were then processed with developer and a formulated surface conditioner and compared to wafers processed with developer and DI water. When analyzed, wafers processed with surface conditioner had a 33% increase in Depth-of-Focus (DOF) and a 25% increase in Critical Normalized Aspect Ratio (CNAR) compared to DI water. Optical proximity effects are often credited for having a first-order influence on pattern collapse. Trench feature data was generated using an Scanning Electron Microscope (SEM) to compare the pattern collapse performance of OptiPattern Clear to DI water. The data strongly suggests optical proximity effects are a second-order factor which OptiPattern® Clear resolves. Defect performance for OptiPattern Clear was measured by comparison with a DI water baseline. A production reticle was used to process wafers patterned with 120 nm L/S with 240 nm of resist. The wafers processed with OptiPattern® Clear had similar defect performance as the DI water.

Pattern collapse and line width roughness reduction by surface conditioner solutions for 248-nm lithography

In this paper, surface conditioners were applied during the post-develop process to extend the capability of 248nm lithography processing below the k1= 0.30 threshold. The interaction between surface conditioner and photoresist was found to be a critical parameter in affecting pattern collapse, line width roughness (LWR), and process latitude. Tailoring the surface interaction properties required balancing between surface conditioners that had weak interactions that improved pattern collapse only marginally, to surface conditions with strong interactions that produced a considerable reduction in LWR but provided no benefit to pattern collapse or process latitude when compared to DI water. The surface conditioners with optimized resist interactions provided significant improvement in all performance parameters including reduced pattern collapse, improved LWR, and enlarged usable process latitude.

Surface conditioning solutions for pattern collapse reduction

Recently, there has been a growing interest in using surface conditioning solutions to solve the pattern collapse challenge. In this study, we investigated both pattern collapse and defect performance of surface conditioning solutions on multiple 193 nm resist systems. While the surface conditioning solutions were able to reduce the pattern collapse with good defect control with a majority of resist systems, it can increase the defect level on certain resist. Shortening the surface treatment step and optimizing the formulation can reduce the defect counts to the control level without compromising pattern collapse performance. This study also demonstrated that the surface conditioning solution is compatible with 248 nm processing, enabling the patterning of 90 nm 1:1.2 pitch lines.

Impact of surfactant in developer and rinse solution on 193-nm lithography performance

In this study, surfactant-formulated developer and rinse solutions were used to enhance the performance of a 193 nm lithography process. The wetting and interfacial characteristics of surfactant-formulated solutions were studied and utilized as a screening tool for optimum formulation. The selected formulation was compared to the non-formulated TMAH development and DI water rinse process. Surfactants in developer and rinse solution significantly reduced pattern collapse, enabling an 86% increase of critical normalized aspect ratio. This corresponds to an increase in the usable resist thickness for an 80 nm 1:1 feature from 179 nm to 332 nm. Additional benefit provided by surfactant formulated process was a 25% improvement on both within-wafer and wafer-to-wafer critical dimension uniformity.

Linewidth roughness reduction at the 55 nm node through combination of classical process optimization and application of surface conditioner solutions

In this paper, the standard ASML process was optimized to reduce LineWidth Roughness (LWR) while minimizing the impact on other process performance criteria such as Depth Of Focus (DOF) and Exposure Latitude (EL). The impact of classical process optimization parameters such as post exposure bake temperature and post exposure bake time were investigated together with less often varied parameters such as hard bake temperature. These parameters were studied in conjunction with novel surface conditioners to reduce LWR. The results show that a significant reduction in the LWR number can be obtained by combining the application of a dedicated surface conditioner solution with the fine tuning of other parameters such as post exposure bake and hard bake temperature. Several process parameters had to be tuned simultaneously to retain a decent process window for the fine tuned process although some EL had to be sacrificed.

Formulated surface conditioners in 50 nm immersion lithography:simultaneously reducing pattern collapse and line-width roughness

With the introduction of immersion lithography into IC manufacturing for the 45nm node, pattern collapse and line width roughness (LWR) remain critical challenges that can be addressed by implementing formulated surface conditioners. Surface conditioners are capable of solving multiple issues simultaneously and are easily integrated into the post-develop photolithography process. In this paper, we assessed the impact and reported our findings using a formulated surface conditioning solution in an immersion lithography process to improve the non-pattern collapse and LWR process windows on 300mm Si wafers having 50 nm L/S features. The non-pattern collapse and LWR process window results were then compared to wafers processed using traditional developer processing methods, a DI Water (DIW) rinse. We report our findings using Focus Exposure Matrix (FEM) wafers having 50nm dense lines/spaces (L/S) and a 2.4:1 aspect ratio to determine the non-collapse and LWR process windows. An ASML TWINSCAN XT:1700TM Scanner and a 6%attPSM mask were used to pattern the FEM and LWR wafers. The wafers were then developed using an optimized developer recipe on an RF3iTM coater-developer track. Each wafer was analyzed and evaluated to determine the impact to CD and LWR with respect to the non-pattern collapse process window Formulated surface conditioners having dual capabilities, reduced pattern collapse and LWR, have demonstrated that multiple ITRS Roadmap goals can be achieved and easily implemented into standard IC processing in order to meet these challenges.

Impact of surfactant in developer on CD performance

Surfactant-formulated developers were utilized to enhance the CD performance for 365nm (I-line), 248nm (DUV) and 193nm resist processing. From one generation to the next, the resist surface becomes more and more hydrophobic, creating the need for enhanced surface wetting. Contact angle measurement of surfactant-formulated developers on different generations of resist surfaces, from 365nm to 157nm resist surfaces, indicated improved wetting. On-wafer testing showed significant improvement on CD uniformity with surfactant-formulated developers for 365nm, 248nm and 193nm processing. Faster development rates were also observed for chemically amplified resist systems, including 248nm, 193nm and 157nm.