Manuel Jimenez

Behavioral Modeling Methods for Switched-Capacitor

Sigma-delta Modulators (SigmaDeltaMs) are cornerstone elements in oversampled analog-to-digital converters and digital-to-analog converters (DAC). Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to its long computational time requirements. Behavioral modeling has become a viable solution to this problem. In this paper, we study styles and issues in the accurate modeling of low-power, high-speed SigmaDeltaMs and introduce two new behavioral models for switched-capacitor (SC) integrators. The first model is based on the SC integrator transient response, including the effects of the amplifier transconductance, output conductance, and the dynamic capacitive loading effect on the settling time. The second model is based on a symbolic node admittance matrix representation of the system. Nonidealities such as jitter, thermal noise, and DAC mismatch are also addressed and included in a dual-band, GSM/WCDMA, second-order, multibit SigmaDeltaM model with individual level averaging. VHDL-AMS and MATLAB Simulink were used as modeling languages. Both models are validated against experimental data, showing competitive results in the signal-to-noise-plus-distortion ratio. A comparative analysis between the proposed and a traditional model is presented, with emphasis on the degrading effects due to the integrator dynamics. Moreover, a general simulation speed analysis of the proposed models is addressed.

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Introduction.- Number Systems and Data Formats.- Microcomputer Organization.- Assembly Language Programming.- Embedded Programming Using C.- Fundamentals of Interfacing.- Embedded Peripherals.- External World Interfaces.- Principles of Serial Communication.- The Analog Signal Chain.-

Modulators

A placement methodology for power optimizing macro block-based VLSI layouts is presented. This technique uses simulated annealing to target solutions with reduced switched capacitance. Its implementation is shown to be consistent and capable of producing competitive layouts whose quality is maintained when problem sizes are scaled up. The results obtained on a set of MCNC benchmarks indicate that power reductions over 16% are possible with increases of less than 1% in delay and total wirelength.

Introduction to embedded systems : using microcontrollers and the MSP430

This paper presents the design of a low voltage, low dropout (LDO) regulator with two different output voltages (1V or 1.8V). The basic function of an LDO is to optimize the battery life of portable devices and to provide a constant output voltage to drive small sub-circuits. The proposed LDO was designed using 0.35/spl mu/m CMOS technology. The design is able to drive a load of up to 50mA with a maximum dropout voltage of only 200mV. A low quiescent current (at no load) of approximately 23/spl mu/A, makes this a low power design.

Integrating a low-power objective into the placement of macro block-based layouts

The Electrical and Computer Engineering (ECE) Department of the University of Puerto Rico at Mayaguez (UPRM) in collaboration with renowned engineering companies has developed and implemented an educational model joining traditional co-op education and undergraduate research experience. The model has evolved into a well-rounded learning program with important benefits for all parties involved: students, academia, and employers. This paper describes the program, presents statistics quantifying its impact, and identifies key elements for the success of the approach.

Design of an adjustable, low voltage, low dropout regulator

Current methodologies for software-level power and energy estimation use a microprocessors power model combined with specialized tools that profile the program under study. These tools commonly rely on real-time program execution or simulations to gather the information needed, a process that usually requires a full set of real run-time data. This work proposes the use of static code simulation as an alternative to analyze and predict the programs behavior. This, in combination with a microprocessors power model, allows to estimate power and energy with only a small amount of run-time data. Furthermore, the low execution time of the proposed method allows for its use as in iterative power optimizers. We present results obtained for a set of representative benchmark programs applied ran on a PowerPC 603e microprocessor. Power and energy estimates with mean absolute errors below 7% and 15%, respectively, are reported for the analyzed test cases.

Undergraduate research and co-op education: a winning combination

We present an algorithmically-aware, high-level partitioning methodology for discrete cosine transforms (DCT) targeted to distributed hardware architectures. The methodology relies on the exploration of alternate DCT formulations as part of the partition optimization process. To the best of our knowledge, no previously proposed DCT algorithm exists that is capable of consistently producing alternate regular formulations for an n-size DCT. Hence, a new Cooley-Tukey-like DCT factorization algorithm was developed to allow exploration of alternate formulations as part of the partitioning optimization process. The use of our factorization mechanism along with a greedy strategy to explore the space of equivalent DCT formulations yielded partitioning solutions with as much as 18% reduction in latency and 83% reduction in run-time as compared to previously proposed regular DCT formulations.

Static simulation: A method for power and energy estimation in embedded microprocessors

Division and square root are important operations in a number of data processing algorithms. They are inherently time consuming operations and can require a significant amount of resources when implemented in hardware. This work reports the development of scalable, floating-point (FP) division and square root operators with adjustable precision, range, and pipeline granularity. An algorithm for pipeline insertion was used for both operators, enabling speeds up to 204MFLOPS when implemented on a Xilinx Virtex II FPGA.

Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures

Accurate measurement of reverse recovery parameters (RRPs) in high-speed, high-power switches and rectifiers is a fundamental task in their test and characterization process. Performing such tests at a wafer-level in laterally diffused MOSFETs (LDMOS) presents several challenges with respect to their test in packaged devices. The handling of prober parasitic impedances, current injection constraints, and automated signal synchronization top the list of issues that need to be addressed. Moreover, making the tests amenable for automated execution just adds more constraints to the problem. This paper proposes a solution for automatic characterization of wafer-level LDMOS RRPs that include reverse recovery time (trr), reverse recovery current (Irr), and storage charge (Qrr). Its implementation has enabled accurate automated parametric wafer-level LDMOS tests at currents as high as 15A and ∂I/∂ts of up to 173A/μs.

Scalable pipeline insertion in floating-point division and square root units

Practical considerations for the design of fully differential OTAs and their switched-capacitor common mode feedback (SC-CMFB) network are presented. Different factors affecting the system performance such as OTA gain, bandwidth, common mode open loop gain and bandwidth, and CMFB parameters are discussed. The impact of varying CMFB capacitances and switch sizes are analyzed by means of transistor level simulations. The results showed that larger capacitance ratios produce slower settling times per cycle. However it is better to keep switch widths and capacitances small since clock feedthrough and charge injection can cause significant errors in the steady state CM Voltage.