Nayda G. Santiago

Impact of source code optimizations on power consumption of embedded systems

Power consumption is an important constraint in the design of battery-operated embedded systems. Minimizing power dissipation may be handled in terms of hardware or software optimizations. Source code-level optimization techniques have been used as an alternative to achieve low power consumption when programming embedded systems. However these techniques should be analyzed with statistical sound methods in order to reach strong conclusions about their real impact on power consumption. In this work, source code optimizations were applied on a set of representative benchmarks for embedded processors (MiBench) to analyze whether the techniques have or not an effect on power dissipation of a set of microprocessor based platforms. Design of experiments techniques (DOE) and analysis of variance (ANOVA) were used to achieve statistical sound conclusions. Results showed that not all optimizations have a significant effect on power consumption, moreover some techniques depend on the target platform where they are run.

A statistical approach for the analysis of the relation between low-level performance information, the code, and the environment

This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design of experiments methods to the identification of relations among different levels in the process of mapping computational operations to high-performance computing systems. Statistical analysis is used for studying different factors that affect the mapping process of scientific computing algorithms to advanced architectures. In particular a case study on the numerical solution of finite element methods for the analysis of conformal antennas for electromagnetic radiation applications was used to test the proposed methodology. The use of statistics for identification of relationships among factors has formalized the solution of the problem and this novel approach allows unbiased conclusions about results. Subset selection based on principal components was used to determine the subset of metrics required to explain the behavior of the system.

High-level optimization for low power consumption on microprocessor-based systems

Power consumption is an important constraint in the design of battery-operated embedded systems. The problem of minimizing power dissipation may be handled in terms of hardware or software optimizations. High-level language optimization techniques appear as an alternative to achieve low power consumption when programming embedded systems. In this work, software optimization techniques were applied to a set of code segments in a high-level language, in order to analyze the effect that source code optimizations have on the power dissipation of microprocessor-based systems. Design of experiments (DOE) techniques were used in order to reach statistical sound conclusions about the actual impact that software optimization techniques have on power consumption.

Active learning in an electronic design automation course

This paper summarizes the rationale behind revision of an electronic design automation course and the resulting learning objectives and course model. Early experiences are highlighted.

An FPGA implementation of image space reconstruction algorithm for hyperspectral imaging analysis

The Image Space Reconstruction Algorithm (ISRA) has been used in hyperspectral imaging applications to monitor changes in the environment and specifically, changes in coral reef, mangrove, and sand in coastal areas. This algorithm is one of a set of iterative methods used in the hyperspectral imaging area to estimate abundance. However, ISRA is highly computational, making it difficult to obtain results in a timely manner. We present the use of specialized hardware in the implementation of this algorithm, specifically the use of VHDL and FPGAs in order to reduce the execution time. The implementation of ISRA algorithm has been divided into hardware and software units. The hardware units were implemented on a Xilinx Virtex II Pro XC2VP30 FPGA and the software was implemented on the Xilinx Microblaze soft processor. This case study illustrates the feasibility of this alternative design for iterative hyperspectral imaging algorithms. The main bottleneck found in this implementations was data transfer. In order to reduce or eliminate this bottleneck we introduced the use of block-rams (BRAMS) to buffer data and have data readily available to the ISRA algorithm. The memory combination of DDR and BRAMS improved the speed of the implementation. Results demonstrate that the C language implementation is better than both FPGAs implementations. Nevertheless, taking a detailed look at the improvements in the results, FPGA results are similar to results obtained in the C language implementation and could further be improved by adding memory capabilities to the FPGA board. Results obtained with these two implementations do not have significant differences in terms of execution time.

Hardware Implementation of Image Space Reconstruction Algorithm using FPGAs

The Image Space Reconstruction Algorithm (ISRA) has been used in hyperspectral imaging applications to monitor changes in the environment and specifically, changes in coral reef, mangrove, and sand in coastal areas. This algorithm is one of the set of iterative methods used in the hyperspectral imaging area to estimate abundance. However, ISRA is highly computational, making it difficult to obtain results in a timely manner. In this paper we present the use of specialized hardware in the implementation of this algorithm, specifically the use of VHDL and FPGAs. The implementation of ISRA algorithm has been divided into hardware and software units. The hardware units were implemented on a Xilinx Virtex II Pro XC2VP30 FPGA and the software was implemented on the Xilinx Microblaze soft processor. This illustrates that this approach is a design alternative for iterative hyperspectral imaging algorithms. The main bottleneck found in this implementations was data transfer.

Integrating fundamental and advanced concepts in a rounded capstone design experience in computer engineering

The Accreditation Board for Engineering and Technology (ABET) defines a capstone design course as an integrating experience that draws together diverse elements of the curriculum and develops student competence by focusing both technical and non-technical skills in solving engineering problems. In a Computer Engineering (CE) curriculum, such integration must include elements of software and hardware design merged in a culminating experience that solves a representative problem, while employing engineering standards and realistic constraints. In this paper we describe the academic setting that made possible this integration through a capstone course structure and project that accommodate the requirements of realistic design experiences without the burden of a multi-semester course addition to the CE curriculum. It presents preliminary courses in Software Engineering and Microprocessor Interfacing that led to this experience, insight into the complexity of the chosen problem, and summarizes the learning experience from the perspectives of both students and professors in hopes that others could benefit from this model.

Low power software techniques for embedded systems running real time operating systems

Power consumption is an important constraint in embedded systems running real time operating systems (RTOS). This study proposes an evaluation of significance of the joint effect of possible factors in the power consumption of RTOS running on small and medium scale embedded systems. Design of experiments techniques (DOE) were used to identify the impact in the power consumption of the system. A case of study is presented with optimizations oriented to dynamic frequency scaling and memory management were applied to FreeRTOS. Experiments allowed us to find relationships between the type of architecture, the workload, and OS optimizations in power reduction.

Abundance estimation algorithms using NVIDIA CUDA technology

Spectral unmixing of hyperspectral images is a process by which the constituents members of a pixel scene are determined and the fraction of the abundance of the elements is estimated. Several algorithms have been developed in the past in order to obtain abundance estimation from hyperspectral data, however, most of them are characterized by being highly computational and time consuming due to the magnitude of the data involved. In this research we present the use of Graphic Processing Units (GPUs) as a computing platform in order to reduce computation time related to abundance estimation for hyperspectral images. Our implementation was developed in C using NVIDIA(R) Compute Unified Device Architecture (CUDATM). The recently introduced CUDA platform allows developers to directly use a GPUs processing power to perform arbitrary mathematical computations. We describe our implementation of the Image Space Reconstruction Algorithm (ISRA) and Expectation Maximization Maximum Likelihood (EMML) algorithm for abundance estimation and present a performance comparison against implementations using C and Matlab. Results show that the CUDA technology produced results around 10 times better than the fastest implementation done on previous platforms.

Integrating novel methodologies, tools, and IT resources for graduate level courses in high performance computing and advanced signal processing algorithms

This work presents an approach at integrating novel methodologies for teaching graduate level courses in the areas of high performance computing (HPC) and advanced signal processing algorithms (ASPA) for computer engineering and computer science and engineering curricula. The novel teaching methodology presented here in high performance computing centers on the use of innovative empirical methods, i.e., exploratory data analysis, experiment design, etc., for studying computer performance, whereas an operator signal algebra approach is considered a novel methodology for the studying of advanced signal processing algorithms. The work also discusses an on going concerted effort at utilizing common tools and IT resources in both courses to provide students a holistic learning experience.