Maogang Wang

Dragon2000: standard-cell placement tool for large industry circuits

In this paper, we develop a new standard cell placement tool, Dragon2000, to solve large scale placement problem effectively. A top-down hierarchical approach is used in Dragon2000. State-of-the-art partitioning tools are tightly integrated with wirelength minimization techniques to achieve superior performance. We argue that net-cut minimization is a good and important shortcut to solve the large scale placement problem. Experimental results show that minimizing net-cut is more important than greedily obtain a wirelength optimal placement at intermediate hierarchical levels. We run Dragon2000 on recently released large benchmark suite ISPD98 as well as MCNC circuits. For circuits which have more than 100 k cells, comparing to iToolsl.4.0, Dragon2000 can produce slightly better placement results (1.4%) while spending much less amount of time (2/spl times/ speedup). This is also the first published placement result on the publicly available large industrial circuits.

Modeling and minimization of routing congestion

Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability most accurately. In this paper, we study the congestion minimization problem during placement. First we point out that the bounding box router used previously is not an accurate measurement of the congestion in the placement. We use a realistic global router to evaluate congestion in the placement stage. This ensures that the final placement is truely congestion minimized. We also propose two new post processing algorithms, the flow-based cell-centric algorithm and the net-centric algorithm. While the flow-based cell-centric algorithm can move multiple cells at the same time to minimize the congestion, it suffers large consumption of memory. Experimental results show that the net-centric algorithm can effectively identify the congested spots in the placement and reduce the congestion. It can produce on an average 7.7% less congestion than the bounding box router method. Finally, we use a final global router to verify that the placement obtained from our algorithm has 39% less congestion than a wirelength-optimized placement obtained by TimberWolf (commercial version 1.3.1).

Congestion minimization during placement

Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is the least understood, however, it models routability most accurately. In this paper, we study the congestion minimization problem during placement. First, we show that a global placement with minimum wirelength has minimum total congestion. We show that minimizing wirelength may (and in general, will) create locally congested regions. We test seven different congestion minimization objectives. We also propose a post processing stage to minimize congestion. Our main contribution and results can be summarized as follows. (1) Among a variety of cost functions and methods for congestion minimization (including several currently used in industry), wirelength alone followed by a post processing congestion minimization works the best and is one of the fastest. (2) Cost functions such as a hybrid length plus congestion (commonly believed to be very effective) do not always work very well. (3) Net-centric post-processing techniques are among the best congestion alleviation approaches. (4) Congestion at the global placement level, correlates well with congestion of detailed placement.

On the behavior of congestion minimization during placement

Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability accurately. In this paper, we study the congestion minimization problem during placement. We introduce the notion of consistent routing model and promote its adoption by placement systems. First, we show that in this model the wirelength objective is indeed a good measure of congestion by establishing that a placement with minimum wirelength has minimum total congestion. We show that minimizing wirelength may (and in general, will) create locally congested regions. We demonstrate that most other congestion related objectives are ill behaved and they should only be used in a post processing step. We then propose several novel congestion minimization objectives. One in particular, called over ow minimization with look-ahead, performs very well and can be computed very e ciently in an incremental manner. At the end, we propose a post processing phase that further improves the congestion. By combining the over ow minimization with look-ahead and the post processing phase, we improve the congestion by more than 40% on the average.

NRG: global and detailed placement

We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the grid size, the placement is carried out in three steps: global placement, detailed placement and final optimization. We will show that the output of the global placement can also serve as a fast and accurate predictor. Current implementation is based on simulated annealing. We have put all algorithms together in a placement package called NRG (pronounced N-er-G). In addition to area minimization, NRG can perform timing-driven placement. Experimental results are strong. We improve TimberWolfs results (version 1.2, the commercial version which is suppose to be better than all university versions including version 7) by about 5%. Our predictor can estimate the wirelength within 10-20% accuracy offering 2-20x speedup compared with the actual placement algorithm.

Multi-center congestion estimation and minimization during placement

As technology advances, more and more issues need to be considered in the placement stage, e.g., wirelength, congestion, timing, coupling. It is very hard to consider all of them together at the same time. Thus it is good if we can optimize one cost function without affecting others. In this paper, we will study methods to optimize congestion in placement without inflicting degradations/violations in other objectives or constraint. We give a mathematical equation to predict the overflow within a region using a normal distribution approximation. According to experiments, this equation does give a good estimation of overflow. We used this equation to find the smallest regions which have enough routing resource to alleviate the congestion and propose the flexible expansion scheme in our multi-center congestion reduction (MC2R) algorithm. Experimental results show that generally there is a correlation between the amount of reduction in congestion and the amount of change made to the placement: the more we change the placement, the more reduction in congestion we will get. However, the flexible expansion scheme is very effective in helping us reduce congestion while making only little change to the placement. Comparing to the full expansion scheme (49% congestion reduction and 6.5% change in placement), the flexible expansion scheme together with MC2 R algorithm can reduce congestion by almost the same amount (42%) with much less change made to the placement. (1.8%).

Dragon2006: blockage-aware congestion-controlling mixed-size placer

In this paper, we develop a mixed-size placement tool, Dragon2006, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partitioning and simulated annealing is used to place very large SoC-style designs containing fixed blockage, movable macro blocks of various sizes and standard cells. Moreover, we have applied several techniques for wirelength optimization, congestion estimation in the presence of blockage and white space allocation for congestion removal.

Congestion reduction during placement with provably good approximation bound

This paper presents a novel method to reduce routing congestion during placement stage. The proposed approach is used as a post-processing step in placement. Congestion reduction is based on local improvement on the existing layout. However, the approach has a global view of the congestion over the entire design. It uses integer linear programming (ILP) to formulate the problem of conflicts between multiple congested regions, and performs local improvement according to the solution of the ILP problem. The approximation algorithm of the formulated ILP problem is studied and good approximation bounds are given and proved. Experiments show that the proposed approach can effectively alleviate the congestion of global routing results. The low computational complexity of the proposed approach indicates its scalability on large designs.

Quality of EDA CAD tools: definitions, metrics and directions

In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.

Multi-way partitioning using bi-partition heuristics

The multi-way partition problem is very important in various applications. In this paper, we use analytical and experimental results to study the k-way partition problem. We introduce the concept of embedding graph for the the k-way partition problem. Based on this concept, we explain different scenarios of using a bi-partition heuristic to solve the k-way partition problem. If C denote the optimal cut cost for the k-way partition problem and the bi-partition heuristics we use are /spl delta/-approximation heuristics, we prove that the cut cost from the hierarchical approach has an approximate upper bound of /spl delta/C/spl middot/log k while the cut cost from the all-way bi-partition, or flat approach, has an upper bound of /spl delta/Ck. This is contrary to some claims made in the recent literature (and CAD tools designed based on it). Experimental results strongly support our theoretical analysis. Our results show that for large target graph, the hierarchical approach is about 77% better than the single-pass all-way bi-partition approach. The all-way bi-partition approach will perform better in a multipass set-up. However, the hierarchical approach is still on average 7.1% better in quality and 144 times faster than the multi-partition all-way bi-partition approach. The main conclusion of this paper is that, contradictary to what has been suggested in literature, hierarchical bi-partitioning is a more effective multi-way partitioning scheme.