Taraneh Taghavi

Dragon2005: large-scale mixed-size placement tool

In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partitioning and simulated annealing is used to place very large SoC-style designs containing thousands of macro blocks of various sizes and millions of standard cells. Macro aware partitioning and techniques to properly handle different bin sizes are required, because of the existence of large macro blocks. Our tool is also a congestion and timing aware placement tool.

Dragon2006: blockage-aware congestion-controlling mixed-size placer

In this paper, we develop a mixed-size placement tool, Dragon2006, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partitioning and simulated annealing is used to place very large SoC-style designs containing fixed blockage, movable macro blocks of various sizes and standard cells. Moreover, we have applied several techniques for wirelength optimization, congestion estimation in the presence of blockage and white space allocation for congestion removal.

Innovate or perish: FPGA physical design

The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. The size and complexity of modern FPGAs has far outpaced the innovations in FPGA physical design. The problems faced by FPGA designers are similar in nature to those that preoccupy ASIC designers, namely, interconnect delays and design management. However, this paper will show that a simple re-targeting of ASIC physical design methodologies and algorithms to the FPGA domain will not suffice. We will show that several well researched problems in the ASIC world need new problem formulations and algorithms research to be useful for todays FPGAs. Partitioning, floorplanning, placement, delay estimation schemes are only some of the topics that need complete overhaul. We will give problem formulations, motivated by experimental results, for some of these topics as applicable in the FPGA domain.

Tutorial on congestion prediction

With the increasing sophistication of circuits and specifically in the presence of IP blocks, new estimation methods are needed in the design flow of large-scale circuits. Up to now, a number of post-placement congestion estimation techniques in the presence of IP blocks have been presented. In this paper we present a unified approach for predicting wirelength, congestion and delay parameters early in the design flow. We also propose a methodology to integrate these prediction methods into the placement framework to handle the large complexity of the designs.

Routing algorithms: architecture driven rerouting enhancement for FPGAs

The routing channels of todays FPGAs consist of wire segments of various types, which allow the use of new techniques to enhance the routability of net segments in channels. In this paper we present an optimal greedy algorithm to switch the tracks that net segments are assigned to. This allows us to enhance the rerouting ability by capturing the features of the routing architecture. Suppose the number of tracks in the channels is given. The goal of this algorithm is to increase the number of routed segments of late rerouting requests. This is a good feature for supporting engineering change order (ECO) type of routing. Supporting ECO routing enables the routing algorithms to deal with later changes in routing requests. We used the routing architecture of VirtexII FPGAs from Xilinx as our target architecture and integrated our algorithm into the VPR FPGA routing tool. The experimental results show that our algorithm makes VPR router capable of handling 28.4% more rerouting for segments that are added to the design later

Congestion Minimization in Modern Placement Circuits

6 In this chapter, we propose a placement tool called Dragon which deploys hierarchical techniques to place large-scale mixed size designs that may contain thousand of macro blocks and millions of standard cells [1, 2, 3]. Min-cut based top-down approach is taken to handle the large complexity of designs and simulated annealing is used to minimize the total wirelength. Min-cut partitioning should be aware of large macro cells and may result in bins with different sizes. During simulated annealing, different bin sizes have to be considered. The techniques discussed in this work can be easily incorporated into any hierarchical placement flow and effectively produce legal final layouts with a short runtime. As VLSI circuits are growing in both size and complexity, not only the half-perimeter wirelength but also congestion need to be emphasized at the placement stage. Congestion is one of the main optimization objectives in global routing. However, the optimization performance is constrained because the cells are already fixed at this stage. A highly congested region in the placement often leads to routing detours around the region, in turn results in a larger routed wirelength. Congested areas can also downgrade the performance of global router and, in the worst case, create an unroutable placement in the fix-die regime [12]. Congestion can be modeled as the summation of linear [15] or quadratic [10] function of difference between routing demand and routing resource. Existing congestion reduction techniques include incorporating congestion into cost function of simulated annealing [10], combining a regional router into

System Level Estimation of Interconnect Length in the Presence of IP Blocks

With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-scale circuits. Up to now, the proposed techniques for wirelength estimation in the presence of IP blocks approached this problem either in a flat framework based on the geometrical structure of the circuit or in a hierarchical framework based on uniform distribution property for standard cells. In this paper, the authors propose a technique for hierarchical derivation of wirelength estimation in the presence of single and multiple blockages using Rents parameter of the circuit by assuming non-uniform probability distribution for standard cells. To measure the accuracy of the estimation, the authors compared the results with the results of placement and routing using a commercial CAD tool. The results illustrate that in the presence of multiple IP blocks, the average error of our technique is less than 8%, as compared to its counterparts with the average error of 35% and 150%

Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks

With the increasing sophistication of circuits and specifically in the presence of IP blocks, new estimation methods are needed in the design flow of large-scale circuits. Up to now, a number of post-placement congestion estimation techniques in the presence of IP blocks have been presented. The authors propose a novel stochastic pre-placement approach for concurrent congestion and wirelength estimation using the Rents exponent of the circuit. The experiments illustrate that the proposed method can quickly and accurately estimate wirelength and congestion. Simulation results show that the average error of the proposed wirelength estimation technique is less than 7%. Moreover, it is shown that in presence of IP blocks using a congestion removal technique based on our congestion estimation method results in 12.8% decrease in overflow on average

Block placement to ensure channel routability

Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total width/height of the chip and optimal routing area can be obtained. The proposed technique utilizes a piecewise linear model of the channel width. Based on this model, we introduce LP formulation to determine the optimal channel width considering pin alignment by balancing the wire length and the channel width.

Routing algorithms: enhancing routability & enabling ECO (abstract only)

The routing channels of todays FPGAs consist of wire segments of various types. This routing architecture makes us capable of exploiting some new techniques to enhance the routability of net segments in channels in order to support engineering change order (ECO). In this paper we present an optimal greedy algorithm to switch the track, which each net segment is assigned to, in order to enhance the routability of newly added nets for enabling ECO. We used the routing architecture of Virtex II FPGAs from Xilinx as our target routing architecture and integrated our algorithm into VPR FPGA routing tool. The experimental result show that the algorithm reduces the number of Tracks by 9% in average. It allows 28.4% more rerouting than the existing router of VPR tool, which is based on Dijkestras maze router algorithm.