Marc-André Cantin

A comparison of automatic word length optimization procedures

This paper presents a comparison of word length determination procedures. It is realized using an automated testbed that exploits a C/C++ fixed-point simulation utility to model the impact of finite word length on overall accuracy. Word length determination procedures find a combination of optimum bit resolutions by computing dissimilarities between fixed-point and floating-point simulation results. The comparison helps to select a procedure that minimizes these dissimilarities and finds an optimal combination of word lengths that meet user specified objectives, in a minimum number of iterations and hardware cost. This comparison was applied on various DSP algorithms.

An automatic word length determination method

A method to determine the word length required by implementations of Digital Signal Processing (DSP) algorithms is presented. The method uses a C/C++ fixed-point simulation tool to model the impact of finite word length on overall accuracy. It finds a combination of quasi-optimum bit resolutions in arbitrary data flow graphs by computing dissimilarities between fixed-point and floating-point simulation results. The selected algorithm minimizes these dissimilarities and finds a combination of word lengths that meets objectives specified by the user. This method is applicable to a wide range of DSP algorithms. It was tested on 2 benchmarks, the fifth order elliptic filter and the Inverse Discrete Cosine Transform (IDCT), and arrived to known optimum solutions.

A comparison of self-organizing neural networks for fast clustering of radar pulses

Abstract Four self-organizing neural networks are compared for automatic deinterleaving of radar pulse streams in electronic warfare systems. The neural networks are the Fuzzy Adaptive Resonance Theory, Fuzzy Min–Max Clustering, Integrated Adaptive Fuzzy Clustering, and Self-Organizing Feature Mapping. Given the need for a clustering procedure that offers both accurate results and computational efficiency, these four networks are examined from three perspectives – clustering quality, convergence time, and computational complexity. The clustering quality and convergence time are measured via computer simulation, using a set of radar pulses collected in the field. Estimation of the worst-case running time for each network allows for the assessment of computational complexity. The effect of the pattern presentation order is analyzed by presenting the data not just in random order, but also in radar-like orders called burst and interleaved.

A Metric for Automatic Word-Length Determination of Hardware Datapaths

A metric for the automatic determination of word lengths required for implementing DSP algorithms is proposed. The metric is capable of handling several error models computed between the fixed-point and the floating-point simulation results to model the impact of finite word lengths on the overall accuracy. It grades all the word-length combinations and guides a procedure towards the optimal solution. This metric was implemented in an automatic word-length determination tool to guide its search for better hardware implementations. It enables the creation of a framework for architecture and platform exploration

A VLSI architecture for fast clustering with fuzzy ART neural networks

The hardware implementation of the fuzzy ART neural network applied to a demanding real time radar signal clustering problem is investigated. To obtain efficient solutions for implementing this neural network with dedicated hardware, the networks algorithm is reformulated, and then a novel fuzzy ART system architecture is proposed. This system architecture is composed of a global comparator and several identical elementary modules (EMs), each one emulating a number of neurons. The general architecture of each EM consists of a local comparator, dividers, neural processors, and a block of memory.

Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm

Theoretical motivations for using a fast and accurate single-tone frequency estimator called the Crozier algorithm are presented. An architectural study shows that with its linear complexity, it is well suited to both hardware and software implementations. It has been implemented on one hardware (Xilinx XCV1000 FPGA) and two software (ARM940T and Pentium III) platforms and their performances are compared.

IP characterization methodology for fast and accurate power consumption estimation at transactional level model

Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like TLM, to estimate power earlier. This paper presents a high-level IP oriented power estimation methodology. The methodology separates the activity of the IP from the implementation. This allows the ability to easily create a model that can be used with different frequencies, layout and implementation technology. By using data gathered from the RTL a model can be created for high-level simulation that can take into account the technology and characteristics of the FPGA device. The methodology is presented in this paper with a processor and its local memory IP from Xilinx. Compared to estimations made at the RTL level, the resulting model gives accurate results of 15% with three to four order speedups and through different implementations.

Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

Traditional register-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin- and cycle-accurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.

Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm

A reformulated Adaptive Resonance Theory (ART) neural network algorithm has recently been implemented in digital hardware. Naturally, the fixed point, fixed word length data format used causes some output differences with respect to floating point computer simulation. These differences are observed when using realistic input data. The effects of input quantization and the accumulation of round off errors in the arithmetic operations making up the algorithm are analyzed. Even a small quantization or round off error can trigger a change in the clustering produced. This does not mean that the clustering is not valid. Indeed, the validity of the clustering can be comparable to that obtained by floating point computer simulation, provided the word length is sufficient. This is verified on realistic input data consisting of radar pulses received from a number of emitters.

A UNIFIED ENVIRONMENT TO ASSESS IMAGE QUALITY IN VIDEO PROCESSING

A new unified environment to analyze hardware implementations of video processing and noise reduction algorithms is proposed and analyzed. Based on an automatic word-length determination tool, it evaluates the implementation costs required to reach a given quality target by performing several tests with noisy images at different noise levels. The unified environment uses a universal image quality index to compute the effect of finite precision on image quality. Also, this unified environment has the capacity to distribute the analysis task over a computer network in order to reduce the required processing latency. This unified environment helps to determine which algorithm requires the lowest implementation cost. Furthermore, the unified environment is useful to explore multiple hardware architectures that can be used to implement a given noise reduction algorithm.