Marc Boulé

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis

Assertion based design, and more specifically, assertion based verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that efficiently generate the checkers from assertions, for their inclusion in the debug phase. We also detail how a checker generator can be used as a means of circuit design for certain portions of self test circuits, and more generally the design of monitoring circuits. Efficient subset partitioning of checkers for a dedicated fixed-size reprogrammable logic area is developed for efficient use of dedicated debug hardware

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug

This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers, as well as the improved metrics relating to the coverage of assertion checkers. The proposed techniques have been successfully incorporated into the MBAC checker generator.

Automata-based assertion-checker synthesis of PSL properties

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers are resource-efficient for use in hardware emulation, simulation acceleration and silicon debug

Incorporating efficient assertion checkers into hardware emulation

Assertion-based verification (ABV) is emerging as a paramount technique for industrial-strength hardware verification, especially through the emerging property specification language (PSL). Since PSL introduces significant overhead to simulators, in this paper we present the infrastructure for hardware emulation capable of supporting ABV. We develop a tool that generates hardware assertion checkers for inclusion into efficient circuit emulation. The MBAC checker generator is outlined, together with the algorithms for optimized assertion-circuit generation. Experiments show that MBAC outperforms the best known checker-generator.

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertionu to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers anre resource-efficient for use in hardwarre emulation, simulation acceleration and silicon debug.

Debug enhancements in assertion-checker generation

Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead.

Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation

In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used assertion-based verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.

Defining and Providing Coverage for Assertion-Based Dynamic Verification

With the emerging predominance of assertion-based dynamic verification, test generation is a key area where assertions can play a bigger role. Generation of test sequences from properties defined by assertions can help in finding failures in corner-cases of the design specification that without assertions may not be possible. As such, we rely on the duality between property checkers and test generators to take advantage of the information present in the assertions for effective test scenarios—a much needed endeavor given the increasing challenges in verification. To undertake such an effort, we first elaborate on the relation between the coverage of the assertion-based specification and the specific coverage metrics over finite nondeterministic automata representing the assertions. We finally present Airwolf-TG that generate test sequences from compact automata produced by the MBAC tool.

Airwolf-TG: A test generator for assertion-based dynamic verification

With the emerging predominance of assertion-based dynamic verification, test generation is a key area where assertions can play a bigger role. We consider the generation of test sequences from properties defined by assertions. Such tests are aimed at finding failures in corner-case scenarios of the design specification that test generation alone, without assertions, may not be able to achieve. As such, we take advantage of the information present in the assertions to help build more effective test scenarios - a much needed endeavor given the increasing challenges in verification. We present algorithms in Airwolf-TG that generate test sequences from efficient and compact automata produced by MBAC tool.

An FPGA based move generator for the game of chess

This paper details the architecture of an FPGA chess-move generator. The design is based on Deep Blues move generator. The inherent differences between ASICs and FPGAs imply many design changes. We present improvements that exploit important FPGA features (lookup-table based logic, routing resources, distributed and block RAM).