Marc R. Faucher

Low-cost testing of high-density logic components

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBMs high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The testers design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches. >

Low cost testing of high density logic components

The authors describe the evolution and architecture of a logic device tester for the next generation of high-density logic components to be produced by IBM at its Essex Junction, Vermont, facility. The tester architecture is based on the design of an existing internal memory tester, rather than on the design of a conventional logic tester. This design point was an evolutionary outcome of a comprehensive logic test strategy development process. That strategy called for inclusion of boundary scan and array built-in self test in each component design, and for adoption of weighted random pattern logic testing (WRPT). WRPT enables tester data volumes to be reduced by two orders of magnitude in comparison with stored pattern logic testing, while simultaneously maintaining high test quality. The resulting tester architecture and design are described in the context of those decisions.<<ETX>>The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBMs high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The testers design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.<<ETX>>